Unexpected behavior with simple dff example - unexpected triggering at time==0

From: https://github.com/cocotb/cocotb/pull/1529#pullrequestreview-387867775

# test_dff.py

import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge

@cocotb.test()
async def test_dff_simple(dut):
    """ Test that d propagates to q """

    clock = Clock(dut.clk, 10, units="us")  # Create a 10us period clock on port clk
    cocotb.fork(clock.start())  # Start the clock

    for i in range(10):
        await RisingEdge(dut.clk)  # Synchronize ourselves with the clock
        val = random.randint(0, 1)
        dut.d <= val  # Assign the random value val to the input port d
        await FallingEdge(dut.clk)
        assert dut.q == val, "output q was incorrect on the {}th cycle".format(i)

  6000.00ns ERROR    cocotb.regression                         regression.py:396  in _score_test                     Test Failed: test_dff_simple (result was ValueError)
                                                                                                                     Traceback (most recent call last):
                                                                                                                       File "/examples/dff_simple/test_dff.py", line 20, in test_dff_simple
                                                                                                                         assert dut.q == val, "output was incorrect on the {}th cycle".format(i)
                                                                                                                       File "/cocotb/handle.py", line 409, in __eq__
                                                                                                                         return self.value == other
                                                                                                                       File "/cocotb/binary.py", line 439, in __eq__
                                                                                                                         return self.value == other
                                                                                                                       File "/cocotb/binary.py", line 296, in value
                                                                                                                         return self.integer
                                                                                                                       File "/cocotb/binary.py", line 287, in integer
                                                                                                                         return self._convert_from[self.binaryRepresentation](self._str)
                                                                                                                       File "/cocotb/binary.py", line 193, in _convert_from_unsigned
                                                                                                                         return int(resolve(x), 2)
                                                                                                                       File "/cocotb/binary.py", line 45, in resolve
                                                                                                                         raise ValueError("Unable to resolve to binary >%s<" % string)
                                                                                                                     ValueError: Unable to resolve to binary >z<
  6000.00ns ERROR    cocotb.regression                         regression.py:227  in tear_down                       Failed 1 out of 1 tests (0 skipped)

[cmarqu]

There is also “The Facts and Fallacies of Verilog Event Scheduling: Is the IEEE 1364 Standard Right or Wrong?”: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.611.4282&rep=rep1&type=pdf

[marlonjames]

In all the simulators tested besides Modelsim or VCS, RisingEdge dumps you before the HDL resolves, so you must wait for ReadWrite or ReadOnly to have the HDL resolve the signals so you can read the correct values. Modelsim and VCS fail when waiting on ReadWrite after RisingEdge.

We should investigate whether Modelsim and VCS infact dump you in ReadWrite after a RisingEdge, or if some other issue is to blame. Assuming that is the case, what should be done about it?

Part of the issue may stem from the fact that dut.clk <= 1 in the custom_clock forked task is just scheduling the clock edge for Scheduler._do_writes() to perform. _do_writes() waits for ReadWrite (and is the first task to run), then updates the signal values. Then other tasks waiting on ReadWrite are run. RisingEdge(dut.clk) is triggered after returning from the ReadWrite callback, before the HDL resolves, since the signal has changed value.

Modelsim and VCS may have issues registering for another cbReadWriteSynch callback with 0 delay right after it was just called.