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Use SB_GB_IO instead of SB_IO+SB_GB

See original GitHub issue

SB_GB_IO has a much lower (and completely predictable!) delay than SB_IO + SB_GB pair we are using now. In fact, using the latter pair has been observed to (rarely) lead to selftest failures due to setup/hold violations on FD pins.

Unfortunately, simply switching to SB_GB_IO completely breaks FX2 timing. I have adjusted the strobes to work (without actually trying to think of a proper solution) in the sb_gb_io branch, but really, a model of the FX2 bus and tests are necessary to fix this properly. See #44.

Issue Analytics

  • State:closed
  • Created 5 years ago
  • Comments:21 (17 by maintainers)

github_iconTop GitHub Comments

1reaction
smunautcommented, Dec 6, 2018

I’ve been looking into the timings between the FX2 and ICE interface.

ICE to FX2

The ICE has a clock-to-out somewhere between 9 and 10 ns. (relative to the if_clk at the fpga pad). The FX2 has requirements for up to 11 ns setup time (depends on which signal) and 0ns hold time.

So this works just fine. The data valid window of the ICE outputs entirely cover the data capture window of the FX2 with plenty of margins. Whatever the ICE outputs will be captured on the next rising clk edge by the FX2.

See diagram below :

ice_to_fx2

FX2 to ICE

The FX2 is a bit under-specified in its clock-to-out. There is only a max value of 11 ns but no minimum value, so we have to assume that the data isn’t valid at all from the clock edge up to 11 ns after it.

In the ICE40 it takes a long time for the clock to go from the pad to the actual SB_IO register, so the data capture window is well after the clock edge has happened. The setup time is -1.3 ns and hold time is 5.6 ns.

So this means that the ICE40 data capture window is right in the middle of the unstable part of the FX2 output 😕 See diagram below.

fx2_to_ice

The best way to solve this would be to use the DDR registers in the SB_IO to capture the window on the falling edge of if_clk and then immediate re-register it in a fabric DFF on the rising edge. This way the data would be captured in the valid zone and the fpga logic would see whatever is output by the FX2 on the next rising edge of if_clk.

Details

Attached the timing report from icecube to get details on the IO timings. Also attached the sources for the wavedrom drawings.

timing.txt fx2_to_ice.json.txt ice_to_fx2.json.txt

0reactions
whitequarkcommented, Apr 2, 2019

@daveshah1 Nevermind, I rebuilt Yosys and the crash came away.

Read more comments on GitHub >

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