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A simple proposal for better generated names
See original GitHub issueAlthough Chisel3 naming is definitely improving, I still find myself having to grep through the generated Firrtl for a wire/reg/module/etc. named _T* every so often.
This process would be a bit more user friendly if the Chisel-generated names were distinguished by type. So wires could be named _W*, registers _R*, modules _M*, and so forth.
I imagine (hope) this would not be a burdensome change, and it would definitely improve readability and ease my use case.
See also my related Firrtl request: ucb-bar/firrtl#469
Issue Analytics
- State:
- Created 7 years ago
- Reactions:2
- Comments:5 (5 by maintainers)
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when I first skimmed the proposal I assumed _M was for memories… which it should be.
This was done in
v3.4.0