bug: should be able to instantiate a memory in a RawModule
See original GitHub issueType of issue: bug report
It used to be possible to instantiate a Mem
or SyncReadMem
in RawModule
without an implicit clock. The 3.5 release broke this.
Now you get a somewhat cryptic error message:
chisel3.internal.ChiselException: Error: No implicit clock.
If the current behavior is a bug, please provide the steps to reproduce the problem: Example from a real chisel project: https://scastie.scala-lang.org/zGQEY02JTBO3zYEtz6Mh5Q
What is the current behavior? Cryptic error message, then elaboration fails:
chisel3.internal.ChiselException: Error: No implicit clock.
What is the expected behavior?
The circuit should successfully elaborate as was the case with older Chisel releases.
Issue Analytics
- State:
- Created a year ago
- Comments:13 (13 by maintainers)
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So maybe this should have been an Option: https://github.com/chipsalliance/chisel3/pull/2333/files#diff-69a38113a9a1186347fec4aa8cdd4b0366b5bac9d5eb4aca99fcf98717844bf4R59
and if it fails we use a “None”, then the warning can say “None” was the implied clock…
The clocks are associated with the port. The code in my example instantiates a memory where the two ports are driven by different clocks. If you think about this in term of verilog, the variable declaration will not be associated with a clock, only the memory updates will be associated with clocks through a
always @posedge clock
block.