Can assign registers from different clock domain

It’s possible to assign a register in a different clock domain than the one it was created in, but the assignment still happens on the register instantiation clock. For example:

val a = Reg(...)
withClock (someDifferentClock) {
  a := somethingElse
}

But a still updates on the enclosing clock, not someDifferentClock.

The register assignment in a different clock domain should probably be an error, as the results are not what would be expected from reading the code.

Type of issue: other enhancement

Impact: API modification

Development Phase: proposal

[aswaterman]

Please don’t change this - we rely upon it extensively. The documentation and scaladoc should just be very clear that the register gets its clock at declaration time, not at assignment time.

[ducky64]

Resolution from the dev meeting today was “working as intended”.

There is also a proposed feature to check unsafe clock domain crossings in FIRRTL (with safe crossings as an annotation), though it not really the same issue (since reconstructing lexical scope information like withClock scopes in FIRRTL is iffy at best).