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Cat rename signal name if it doesn't suggest name yet

See original GitHub issue

Type of issue: bug report

Impact: no functional change

Development Phase: request

If the current behavior is a bug, please provide the steps to reproduce the problem:

package chisel3
  
import chisel3._
import chisel3.stage.ChiselStage
import chisel3.util._

class Top extends RawModule {
  val in0 = IO(Input(UInt(1.W)))
  val in1 = IO(Input(UInt(1.W)))
  val in2 = IO(Input(UInt(1.W)))
  val out = IO(Output(UInt(3.W)))

  out := Cat(in2, in1, in0)
}

object Main extends App {
  (new ChiselStage).emitVerilog(new Top, args)
}

What is the current behavior?

module Top(
  input        lo,
  input        hi_lo,
  input        hi_hi,
  output [2:0] out
);
  wire [1:0] hi = {hi_hi,hi_lo}; // @[Cat.scala 30:58]
  assign out = {hi,lo}; // @[Cat.scala 30:58]
endmodule

What is the expected behavior?

I found that SeqUtils would suggest named signal if it hasn’t suggested_name yet.

https://github.com/chipsalliance/chisel3/blob/4b7499f7c6287c696111bd7c6ee060f33f667419/core/src/main/scala/chisel3/SeqUtils.scala#L29-L35

I wonder why would rename signal in SeqUtils

I change to as follow:

      val lo = asUInt(in.slice(0, in.length/2))
      val hi = asUInt(in.slice(in.length/2, in.length))
      hi ## lo

It generates:

module Top(
  input        in0,
  input        in1,
  input        in2,
  output [2:0] out
);
  wire [1:0] _T = {in2,in1}; // @[Cat.scala 30:58]
  assign out = {_T,in0}; // @[Cat.scala 30:58]
endmodule

Please tell us about your environment:

  • version: 3.5-SNAPSHOT
  • OS: Ubuntu 18.04

What is the use case for changing the behavior?

Issue Analytics

  • State:closed
  • Created 2 years ago
  • Reactions:1
  • Comments:10 (10 by maintainers)

github_iconTop GitHub Comments

1reaction
ekiwicommented, Jul 7, 2021

Even with the current binary ops, it should be able to add a lower optimization pass to remove intermediates nodes and generate something like:

I thought we already had a pass that does that. @jackkoenig , do you know why it doesn’t seem to do anything in this case? https://github.com/chipsalliance/firrtl/blob/master/src/main/scala/firrtl/transforms/CombineCats.scala#L53

1reaction
jackkoenigcommented, Jul 6, 2021

This is mea culpa. In the refinements to the naming plugin behavior in v3.4.1, I changed how autoNameRecursively works which required basically raising the priority of .autoSeed for when it’s used in user code. The mistake was that we also use .autoSeed ourselves in Cat. Not 100% sure on the fix off the top of my head but that’s the source of this bug.

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