Chisel does not generate error if size argument is not .W in RegInit

Type of issue: bug report Impact: no functional change Development Phase: request

What is the current behavior? If I instantiate a register this way :

val sizeFrame = 30
val writeFrame = RegInit(0.U(sizeFrame))

Chisel compile without problem. But the size of writeFrame register will be 1.

I think it’s a chisel bug, because width parameter must be suffixed by ‘.W’.

What is the expected behavior? In my opinion, the correct way to instantiate my register is :

val sizeFrame = 30
val writeFrame = RegInit(0.U(sizeFrame.W))

And the declaration given at the begining should generate an error.

Please tell us about your environment: - version: 3.1.8 - OS: Linux Debian 4.9.0-9-amd64 #1 SMP Debian 4.9.168-1+deb9u5 (2019-08-11) x86_64 GNU/Linux

[jackkoenig]

8.U(3) is a huge wart that merits fixing. Removing indexing with Int would fix it but is a pretty draconian change that would require updating a lot of code (indexing Wires, Regs and the like). There are a couple of other approaches we could do:

• I tried to specifically deprecate (for removal) indexing a literal immediately. It’s a little tricky but it could maybe work: https://github.com/chipsalliance/chisel3/compare/deprecate-literal-bit-extract
• @albert-magyar did a proof of concept of making this a linter error using ScalaFix: https://github.com/chipsalliance/chisel3/pull/1449

[ducky64]

From the example in #871

val foo = 0.U // declare a UInt whose value is 0
val bar = foo(sz) // extract bit sz from foo

Basically, from a Scala operations point of view, it looks like a literal chained with a bit extract, which is legal and apparently in use - and which is why it’s so hard to fix.

One solution might be the use of macros (or a linter) to detect and warn on style-based anti-patterns like this. Or we might define a .U(int) function that is deprecated / errors and requires users to introduce parens to make chained literal - bit extract operations explicit.