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emitVerilog on the ChiselStage object

See original GitHub issue

Type of issue: feature request

Impact: API addition (no impact on existing code)

emitVerilog on the ChiselStage companion object should generate a Verilog file (like the class function).

Furthermore, having the args in the object method would be nice too, as one most of the time wants to specify the target folder.

Issue Analytics

State:
Created 3 years ago
Reactions:1
Comments:5 (5 by maintainers)

Top GitHub Comments

1reaction

schoeberlcommented, May 5, 2021

I would propose to have then two methods: emitVerilog() to write a file (returning nothing, i.e., Unit) and getVerilog() returning just the string. Where to put it? Maybe on an object Chisel3? However, this is a method that does something with a (new) module. So logically it should be a method on Module.

0reactions

schoeberlcommented, May 21, 2021

Could we move stage.* into core? In that case we could simple call the relevant functions from RawModule.

Top Results From Across the Web

how to set generated directory of emitVerilog? - Stack Overflow

Set the arguments as a call to the ChiselStage . Below is an example. This will put the Verilog and FIRRTL in the...

chisel3/ChiselStage.scala at master - GitHub

chisel3/src/main/scala/chisel3/stage/ChiselStage.scala ... final def emitVerilog( ... object ChiselMain extends StageMain(new ChiselStage).

chisel3.stage.ChiselStage - Chisel/FIRRTL

class ChiselStage extends Stage with PreservesAll[Phase] ... final def emitVerilog(gen: ⇒ RawModule, args: Array[String] = Array.empty, ...

freechipsproject/chisel3 - Gitter

seldridge Frederick HONG (Gitter): emitVerilog is a helper utility to run ChiselStage.execute with specific parameters. Internally, Chisel converts command line ...

import chisel3.stage.ChiselStage // z = s ? i1 : i0 class Mux2[T

... io.s) } println((new ChiselStage).emitVerilog(new MuxTest(9, 8))) - Scastie ... object Mux2 { ... println((new ChiselStage).emitVerilog(new MuxTest(9, ...