loadMemoryFromFile() should place readmemh() inline for better compatibility
See original GitHub issueloadMemoryFromFile()
creates a separate file and uses a SV bind statement. A simple example:
import chisel3._
import chisel3.util.experimental.loadMemoryFromFile
class Foo(val bits: Int, val size: Int, filename: String) extends Module {
val io = IO(new Bundle {
val nia = Input(UInt(bits.W))
val insn = Output(UInt(32.W))
})
val memory = Mem(size, UInt(32.W))
io.insn := memory(io.nia >> 2);
loadMemoryFromFile(memory, filename)
}
object FooObj extends App {
chisel3.Driver.execute(Array[String](), () => new Foo(32, 1024, "insns.hex"))
}
# cat Foo.Foo.memory.v
module BindsTo_0_Foo(
input clock,
input reset,
input [31:0] io_nia,
output [31:0] io_insn
);
initial begin
$readmemh("insns.hex", Foo.memory);
end
endmodule
bind Foo BindsTo_0_Foo BindsTo_0_Foo_Inst(.*);
Yosys doesn’t like this, and likely there are other tools that don’t either. Is there any reason we don’t just place it inline?
Issue Analytics
- State:
- Created 4 years ago
- Reactions:2
- Comments:18 (17 by maintainers)
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@antonblanchard check out https://github.com/chipsalliance/firrtl/pull/2107. I’ve added a new annotation allowing inline readmem in Verilog emiter.
Your sample code would become:
that would generate the appropriate:
It would allow also configuration for binary files instead of hex, like:
and output
Opened #2260 to address this.