parameterization to the name of IO

Could you enlight me how to transmit a name to the IO by parameter?

class SRAMIO(my_np:Int=3, nm:String="ram1") extends Bundle {
  val a = Input(Bool())
  val b_$nm = Input(Vec(my_np,UInt(2.W)))
}

class sram extends Module {
  val io = IO(new SRAMIO(4,"ram1"))
}

how can I tell it the $nm is my parameter?

[jackkoenig]

I see. This is where I think something like setName comes into play, although there does need to be a distinction between setting the name of the final Verilog wire vs. more of a local naming.

[ducky64]

String interpolation in wire names seems like what the original example was trying to do.