sub field assignment

Type of issue: bug report

Impact: Chisel 2 code needs changes

Development Phase: request

If the current behavior is a bug, please provide the steps to reproduce the problem:

assign subfields to a register (worked in Chisel 2):

  val shiftReg = RegInit(0x7ff.U)
...
      when(io.channel.valid) {
        shiftReg(0) := 0.U // start bit
        shiftReg(8, 1) := io.channel.data // data
        shiftReg(10, 9) := 3.U // two stop bits

workaround:

        shiftReg := Cat(Cat(3.U, io.channel.data), 0.U) // two stop bits, data, one start bit

What is the current behavior?

[error] (run-main-0) chisel3.internal.ChiselException: Cannot reassign to read-only chisel3.core.Bool@74 [error] chisel3.internal.ChiselException: Cannot reassign to read-only chisel3.core.Bool@74 [error] at chisel3.internal.throwException$.apply(Error.scala:13) [error] at chisel3.core.Data.connect(Data.scala:296) [error] at chisel3.core.Data.$colon$eq(Data.scala:365) [error] at uart.Tx$$anonfun$1$$anonfun$apply$mcV$sp$2$$anonfun$apply$mcV$sp$3.apply$mcV$sp(Uart.scala:55)

What is the expected behavior?

Work like in Chisel 2 or have an explanation in the porting Chisel 2 to 3 document.

Please tell us about your environment:

Mac

[juliusbaxter]

Agree vecs and bundles are nice but you don’t always have them set up to access individual bits, so it’s inconvenient.

I think the main argument against the removal of subword assignment is consistency. If I can get a subword from a value, I should also be able to set it. Inconsistencies like this are frustrating for the user.

[tdb-alcorn]

+1 I’m generating ultra-wide buses to get around the problem of many Vecs slowing down the Chisel compiler, and it would be great to be able to assign to subwords. Currently I’m working around this by using verilog black boxes to subword assign instead (very hacky)