Test Failed with chisel-testers
See original GitHub issueI got a problem when running tests whit chisel-testers. I used ComplexMemoryTester program from https://github.com/freechipsproject/chisel-testers/blob/master/src/test/scala/examples/ComplexMemoryLoadingSpec.scala to load a file from memory. This is the code:
Class MemoryShape extends Bundle {
val a = UInt(65536.W)
}
class HasComplexMemory(memoryDepth: Int) extends Module {
val io = IO(new Bundle {
val address = Input(UInt(log2Ceil(memoryDepth).W))
val value = Output(new MemoryShape)
val Buffer = Output(Vec(100, UInt(32.W)))
})
val H = new ArrayBuffer[UInt]()
for ( k <- 0 until 100) {
H += 0.asUInt(32.W) }
val memory = Mem(memoryDepth, new MemoryShape)
loadMemoryFromFile(memory, "test_run_dir/complex_mem_test/cameraman")
io.value := memory(io.address)
io.Buffer := H
}
class HasComplexMemoryTester(c: HasComplexMemory) extends PeekPokeTester(c) {
for(addr <- 0 until 65536) {
poke(c.io.address, addr)
step(1)
println(f"peek from $addr ${peek(c.io.value.a)}%x")
poke(c.io.Buffer(addr), addr )
println(peek(c.io.Buffer(addr)).toString)
}
println("Done compiling")
}
class ComplexMemoryLoadingSpec extends FreeSpec with Matchers {
"memory loading should be possible with complex memories" - {
val targetDirName = "test_run_dir/complex_mem_test"
FileUtils.makeDirectory(targetDirName)
val path1 = Paths.get(targetDirName + "/cameraman_a")
Files.copy(getClass.getResourceAsStream("/cameraman.txt"), path1, REPLACE_EXISTING)
"should work with verilator" in {
iotesters.Driver.execute(
args = Array("--backend-name", "verilator", "--target-dir", targetDirName, "--top-name", "complex_mem_test"),
dut = () => new HasComplexMemory(memoryDepth = 65536)
) { c =>
new HasComplexMemoryTester(c)
} should be(true)
}
}
}
After running the test some errors appear, the test failed and the simulation stops. This is the complete output:
[info] Done compiling.
[info] [0.008] Elaborating design...
[info] [0.455] Done elaborating.
Total FIRRTL Compile Time: 1975.7 ms
cd /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test && verilator --cc HasComplexMemory.v --assert -Wno-fatal -Wno-WIDTH -Wno-STMTDLY -O1 --top-module HasComplexMemory +define+TOP_TYPE=VHasComplexMemory +define+PRINTF_COND=!HasComplexMemory.reset +define+STOP_COND=!HasComplexMemory.reset -CFLAGS "-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h" -Mdir /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test -f /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test/firrtl_black_box_resource_files.f --exe /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test/HasComplexMemory-harness.cpp --trace
make: Entering directory '/home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test'
g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h -c -o HasComplexMemory-harness.o /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test/HasComplexMemory-harness.cpp
g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h -c -o verilated.o /usr/local/share/verilator/include/verilated.cpp
g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h -c -o verilated_vcd_c.o /usr/local/share/verilator/include/verilated_vcd_c.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VHasComplexMemory.cpp VHasComplexMemory___024unit.cpp > VHasComplexMemory__ALLcls.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VHasComplexMemory__Trace.cpp VHasComplexMemory__Syms.cpp VHasComplexMemory__Trace__Slow.cpp > VHasComplexMemory__ALLsup.cpp
g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h -c -o VHasComplexMemory__ALLsup.o VHasComplexMemory__ALLsup.cpp
g++ -I. -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h -c -o VHasComplexMemory__ALLcls.o VHasComplexMemory__ALLcls.cpp
ar: creating VHasComplexMemory__ALL.a
Archiving VHasComplexMemory__ALL.a ...
ar r VHasComplexMemory__ALL.a VHasComplexMemory__ALLcls.o VHasComplexMemory__ALLsup.o
ranlib VHasComplexMemory__ALL.a
g++ HasComplexMemory-harness.o verilated.o verilated_vcd_c.o VHasComplexMemory__ALL.a -o VHasComplexMemory -lm -lstdc++
make: Leaving directory '/home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test'
sim start on Dell at Sat Sep 28 01:53:11 2019
inChannelName: 00017728.in
outChannelName: 00017728.out
cmdChannelName: 00017728.cmd
STARTING test_run_dir/complex_mem_test/VHasComplexMemory
Enabling waves..%Error: test_run_dir/complex_mem_test/cameraman_a:1: $readmem file syntax error
Aborting...
[info] ComplexMemoryLoadingSpec:
[info] memory loading should be possible with complex memories
[info] - should work with verilator *** FAILED ***
[info] chisel3.iotesters.TestApplicationException: test application exit - exit code 134
[info] at chisel3.iotesters.SimApiInterface.throwExceptionIfDead(SimApiInterface.scala:98)
[info] at chisel3.iotesters.SimApiInterface.chisel3$iotesters$SimApiInterface$$mwhile(SimApiInterface.scala:107)
[info] at chisel3.iotesters.SimApiInterface$$anonfun$start$3.apply$mcVI$sp(SimApiInterface.scala:268)
[info] at scala.collection.immutable.Range.foreach$mVc$sp(Range.scala:160)
[info] at chisel3.iotesters.SimApiInterface.start(SimApiInterface.scala:266)
[info] at chisel3.iotesters.SimApiInterface.<init>(SimApiInterface.scala:325)
[info] at chisel3.iotesters.VerilatorBackend.<init>(VerilatorBackend.scala:295)
[info] at chisel3.iotesters.setupVerilatorBackend$.apply(VerilatorBackend.scala:284)
[info] at chisel3.iotesters.Driver$$anonfun$execute$1$$anonfun$apply$mcZ$sp$1.apply$mcZ$sp(Driver.scala:56)
[info] at chisel3.iotesters.Driver$$anonfun$execute$1$$anonfun$apply$mcZ$sp$1.apply(Driver.scala:39)
[info] ...
[info] ScalaTest
[info] Run completed in 1 minute, 53 seconds.
[info] Total number of tests run: 1
[info] Suites: completed 1, aborted 0
[info] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0
[info] *** 1 TEST FAILED ***
[error] Failed: Total 1, Failed 1, Errors 0, Passed 0
[error] Failed tests:
[error] util.ComplexMemoryLoadingSpec
[error] (Test / testOnly) sbt.TestsFailedException: Tests unsuccessful
Can someone explain the error or help me to fix it please.
Issue Analytics
- State:
- Created 4 years ago
- Comments:7 (5 by maintainers)
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I think you are close to getting this to work. There are two problems. Problem1: The io.Buffer. This is not related to memory.
It looks like you would like to have 100 32bit registers that you can write to and read from.
As declared Buffer in your code is Output, even though testers will let you poke it this will result in a run-time error. The way you are initializing is also problematic. I think it would be better (although I am not certain of your use-case) to do something like the following which allocates a bank of registers to hold the values you poke in. The ArrayBuffer you initialize is pointing at literal values, which cannot be changed. The
H := ...
you had before does not do what you would like,it compiles but will also cause run-time problem.and your tester code will look like
Problems with memory will be addressed in the next comment
The specific error
"$readmem file syntax error"
is a Verilator error indicating, in my understanding, that the file pointed to by$readmemh
or$readmemb
has a bad format.If you are using
loadMemoryFromFile
with the hex option (the default), this will map to$readmemh
. The file should then look like something like: