instance different verilog module when constant propagation.

Type of issue: other enhancement

What is the use case for changing the behavior?

1. optimize the constant propagating behavior by replace xor(a,1) to not(a) etc,
2. instance different verilog module when some ports are tie 0/1 rather than single instance with constant as input.

Impact: API modification Development Phase: request

Here is the example code by chisel3

import chisel3._

trait ConstantPropagationTest {
  class CSAOutBundle extends Bundle {
    val s: UInt = UInt(32.W)
    val c: UInt = UInt(32.W)
  }

  def csa(a: UInt, b: UInt, c: UInt): CSAOutBundle = {
    // the reason I use Module here is I wanna keep the circuit hierarchy. 
    val m = Module(new Module {
      val io = IO(new Bundle {
        val a = Input(UInt(32.W))
        val b = Input(UInt(32.W))
        val c = Input(UInt(32.W))
        val out = Output(new CSAOutBundle)
      })
      val a = Wire(Vec(32, Bool()))
      val b = Wire(Vec(32, Bool()))
      val c = Wire(Vec(32, Bool()))
      val cOut = Wire(Vec(32, Bool()))
      val sOut = Wire(Vec(32, Bool()))
      a := io.a.asTypeOf(Vec(32, Bool()))
      b := io.b.asTypeOf(Vec(32, Bool()))
      c := io.c.asTypeOf(Vec(32, Bool()))
      io.out.s := sOut.asTypeOf(UInt(32.W))
      io.out.c := cOut.asTypeOf(UInt(32.W))
      override def desiredName = "csa"
      for(i <- 0 to 31) {
        sOut(i) := a(i) ^ b(i) ^ c(i)
        cOut(i) := {
          i match {
            case j if j == 0 => false.B
            case default => (a(default - 1) && b(default - 1)) || (b(default - 1) && c(default - 1)) || (a(default - 1) && c(default - 1))
          }
        }
      }
    })
    m.io.a := a
    m.io.b := b
    m.io.c := c
    m.io.out
  }
}

class ConstantTester(dual: Boolean) extends Module
  with ConstantPropagationTest {
  val io = IO(new Bundle {
    val a = Input(UInt(32.W))
    val b = Input(UInt(32.W))
    val out0 = Output(new CSAOutBundle)
    val out1 = Output(new CSAOutBundle)
  })
  val c = WireInit("h1234abcd".U)
  io.out0 := csa(io.a, io.b, c)
  io.out1 := {
    dual match {
      case i if i => csa(c, io.a, io.b)
      case i if !i => DontCare
  }}
}

object ConstantTesterEmitter extends App {
  chisel3.Driver.execute(
    Array("-td", "./constantTesterDualInstance",
    ),
    () => new ConstantTester(true))
  chisel3.Driver.execute(
    Array("-td", "./constantTesterSingleInstance",
    ),
    () => new ConstantTester(false))
}

while propagating a "h1234abcd".U to one csa, the emitted verilog will just omit the constant port, and tie constant inside verilog(port still exist in firrtl). However the while instance two modules, these enhancement won’t exist, the emitted verilog will only have one module, and propagating the constant to port. And by the way the xor constant optimize will give a logic like this:

assign _T_730 = a_7 ^ b_7; // @[PlayGround.scala 29:25]
assign sOut_7 = _T_730 ^ 1'h1; // @[PlayGround.scala 29:32]

obviously, sOut_7 = ! _T_730

[jackkoenig]

Ah yes I think that is the right solution; glad you were able to resolve the issue!

[jackkoenig]

The issue is that this is the desired behavior. Missing out on some amount of constant propagation is nothing compared to the benefits of hierarchical place and route.

Can you elaborate a bit on how big of an issue this is for you? Generally the FIRRTL optimizations are intended to improve performance of downstream simulators and synthesis tools, as well as improve integration with existing tools to avoid common lint errors. We don’t pretend to provide full optimization functionality, leaving that to the actual synthesis tools. Is there a particular tool or flow you’re having trouble integrating with?