PadWidths: generates illegal widths for Dshl

This line in PadWidths ensures that the argument e width of a dshl is the same as its result width: https://github.com/freechipsproject/firrtl/blob/master/src/main/scala/firrtl/passes/PadWidths.scala#L46

    case Dshl =>
        // special case as args aren't all same width
        ex copy (op = Dshlw, args = Seq(fixup(width(ex.tpe))(ex.args.head), ex.args(1)))

(i.e. Result Width == w_e instead of Result Width == w_e + 2^(w_n) - 1)

This is incorrect according to the firrtl spec:

I would suggest just removing this case altogether. However, I am not sure why it was added in the first place.

@donggyukim and @jackkoenig, maybe you can comment on this.

[jackkoenig]

IMO we just need to move the dshlw injection into the Verilog emitter

[ekiwi]

Are you sure? It’s taking the width of ex, which should already include the +2^n-1, since this runs after InferWidths.

The problem is that after we extend e to be the same width as the result (i.e., e_w == Result Width) the equation given in the spec (Result Width == w_e + 2^(w_n) - 1) is no longer true.

In other words, once we extend w such that w_e is equivalent to the Result Width, w_n must be 1 in order for the equation from the spec to hold true. Of course w_n is not always 1, thus we get an ill-typed expression for any n that is wider than 1.