Support for asynchronously-resettable registers

FIRRTL is currently only capable of emitting registers with synchronous reset. This is often OK, but sometimes an asynchronous reset is desirable (e.g., see our recent discussion at ucb-bar/rocket-chip#190, as well as previous discussion from a variety of users). Ultimately, the designer should have the flexibility to choose which type of reset to instantiate. (See this classic discussion of the issue for more detail.)

Asynchronously-resettable flip-flops are a common verilog design idiom and are well-supported by EDA tools. ucb-bar/chisel#549 has a good writeup of the desired feature; I’ve copied and cleaned up the code example here for convenience. The option to select the reset polarity would also be nice.

always @(posedge clk or posedge reset) begin
  if (reset) begin //async-resettable flops
    flop1 <= FLOP1_RESET_VALUE;
    flop2 <= FLOP2_RESET_VALUE;
  end else // D -> Q state updates for async-resettable flops
    flop1 <= flop1_next;
    flop2 <= flop2_next;
  end
end

always @(posedge clk) begin
  if (reset) begin //sync-resettable flops
    flopA <= FLOPA_RESET_VALUE;
    flopB <= FLOPB_RESET_VALUE;
  end else begin // D -> Q state updates for sync-resettable flops and flops with no reset
    flopA <= flopA_next;
    flopB <= flopB_next;
    flopC <= flopC_next; // flopC has no sync or async reset
  end
end

[janboeye]

@azidar Why this feature is low priority? If we want to use Chisel in ASIC chip, this is a must-have feature. In this stage, is there any workaround for this? Thanks a lot!

[azidar]

The low priority tag was determined by user interest - if there is more significant interest, then we can certainly make it a high priority.