Why is ToMemIR restricted to at most 1 read or RW port?

Type of issue: bug report | feature request

From ToMemIR.scala:

/** Annotates sequential memories that are candidates for macro replacement.
  * Requirements for macro replacement:
  *   - read latency and write latency of one
  *   - only one readwrite port or write port
  *   - zero or one read port
  */

ReplSeqMem seemed to be silently doing nothing/failing on sequential memories with >1 read port, so upon further investigation it turns out that ToMemIR has an artificial restriction (e.g. m.readers.length == 1) on the number of ports it supports.

Just as a local experiment, I lifted the port count restriction and nothing bad immediately jumped out (i.e. ReplSeqMem seems to create a blackbox memory with the right number of ports, indexed e.g. R0, R1, etc). Was there a particular reason that the pass is restricted to only 1 read or 1 write/rw port for a given memory?

The restriction is inherited from the original PR (#265) that introduced this functionality and a quick search through the history of this code + the original PR didn’t yield any obvious explanations.

What is the use case for changing the behavior? I wanted to use ReplSeqMem to blackbox a memory that turned out to have >1 read port but the pass silently ignored it until I dug a bit into the memory-replacement passes’ code in FIRRTL.

Impact: API addition (no impact on existing code)

Development Phase: request | proposal

[kammoh]

Is this issue on the radar at all? What is the recommended workaround to use dual-port memories?

[sequencer]

@kammoh maybe only BlackBox can workaround 😦 just come across to this issue again.