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can't get signal under generate block with vcs, using systemVerilog

See original GitHub issue

when I want to capture a signal under generate block,like this: in sv file: for(i=0; i<2; i=i+1) begin : PACKET my_module module1(...)

in cocotb test: topmodule.PACKET[0].module1

I run make: make SIM=vcs it runs wrong and log:

File "/usr/local/lib64/python3.6/site-packages/cocotb/handle.py", line 306, in __getattr__
raise AttributeError("%s contains no object named %s" % (self._name, name))
 AttributeError: topmodule contains no object named PACKET

so, how to get a signal under generate block with vcs?

cocotb environment: simulator and verison: vcs Version O-2018.09-SP python version: 3.6.8

Issue Analytics

State:
Created 3 years ago
Comments:12 (10 by maintainers)

Top GitHub Comments

1reaction

marlonjamescommented, Nov 11, 2020

The workaround in #2143 is only compiled for Icarus. If vpi_handle_by_name doesn’t resolve the vpiGenScopeArray handle, the iteration over parent workaround may work. You could try adding a check for VCS to: https://github.com/cocotb/cocotb/blob/9df43e5c0a797299ff5abc994da7cbbb31756e5e/cocotb/share/lib/vpi/VpiImpl.cpp#L305

1reaction

cmarqucommented, Nov 11, 2020

Unfortunately, I don’t believe it’s fixed in master, I still see the problem with VCS in test_array with TESTCASE=test_discover_all. I’ll try to give more information soon.

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