Icarus Verilog failure "sorry: Format 1 not implemented for getting real values."
See original GitHub issueAs of today I’m getting the following error on Icarus Verilog master (5d97405724d7755ecfbe2bfc25f6e6e81f2d029a):
2022-05-17T18:53:51.1617134Z /usr/local/bin/iverilog -o sim_build/sim.vvp -D COCOTB_SIM=1 -s sample_module -f sim_build/cmds.f -g2012 /home/runner/work/cocotb/cocotb/tests/test_cases/issue_120/../../../tests/designs/sample_module/sample_module.sv
2022-05-17T18:53:51.3888688Z MODULE=issue_120 TESTCASE= TOPLEVEL=sample_module TOPLEVEL_LANG=verilog \
2022-05-17T18:53:51.3889876Z /usr/local/bin/vvp -M /home/runner/work/cocotb/cocotb/.nox/release_test_sim-sim-icarus-toplevel_lang-verilog-gpi_interface-vpi/lib/python3.8/site-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
2022-05-17T18:53:51.3935770Z -.--ns INFO gpi ..mbed/gpi_embed.cpp:109 in set_program_name_in_venv Using Python virtual environment interpreter at /home/runner/work/cocotb/cocotb/.nox/release_test_sim-sim-icarus-toplevel_lang-verilog-gpi_interface-vpi/bin/python
2022-05-17T18:53:51.4119241Z -.--ns INFO gpi ../gpi/GpiCommon.cpp:99 in gpi_print_registered_impl VPI registered
2022-05-17T18:53:51.4752447Z 0.00ns INFO cocotb Running on Icarus Verilog version 12.0 (devel)
2022-05-17T18:53:51.4755874Z 0.00ns INFO cocotb Running tests with cocotb v1.7.0.dev0 from /home/runner/work/cocotb/cocotb/.nox/release_test_sim-sim-icarus-toplevel_lang-verilog-gpi_interface-vpi/lib/python3.8/site-packages/cocotb
2022-05-17T18:53:51.4756472Z 0.00ns INFO cocotb Seeding Python random module with 1652813631
2022-05-17T18:53:51.6018398Z 0.00ns INFO cocotb.regression Found test issue_120.issue_120_scheduling
2022-05-17T18:53:51.6019952Z 0.00ns INFO cocotb.regression running issue_120_scheduling (1/1)
2022-05-17T18:53:51.6030760Z sorry: Format 1 not implemented for getting real values.
2022-05-17T18:53:51.6031850Z vvp: vpi_priv.cc:882: void vpip_real_get_value(double, s_vpi_value*): Assertion `0' failed.
Most likely the regression window is closer to the bad commit, probably no more than a day or two of commits.
FYI @steveicarus Maybe you see the issue right away. Otherwise I’ll try to narrow the regression window in the coming days and file an upstream issue.
Issue Analytics
- State:
- Created a year ago
- Comments:5 (2 by maintainers)
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I did a
git bisect
:iverilog PR: https://github.com/steveicarus/iverilog/pull/714
sample_module.sv
is used in many of our tests, and it has a parameter of typereal
: https://github.com/cocotb/cocotb/blob/be1c95994e8143cdad481a65eea3a2be5db57e3f/tests/designs/sample_module/sample_module.sv#L42For some reason the VCD dumping attempts to get the value in the unsupported format
vpiBinStrVal
.Can you help us out by following the guidelines and attach a small, complete working (failing) example program? I will look into it, since I was the one who implemented this commit. I have a pretty good idea of what’s going on.
On Tue, May 17, 2022 at 3:01 PM Marlon James @.***> wrote:
– Steve Williams @.*** @.***>