Verilator Double-Triggering

I’ve run into a bug where rising edges of clocks will double-trigger, when using Verilator as a simulator.

Here is a minimum reproduction of the design that causes the issue:

module test(input wire clk);
    reg clkdiv2;
    always @(posedge clk) begin
        clkdiv2 <= ~clkdiv2;
    end
endmodule

See this gist for my full test setup.

I can’t seem to get the example to trigger at all in iverilog, so I don’t entirely know if it’s Verilator or CocoTB. I’m assuming iverilog is optimizing out clkdiv2 but I’m not sure how to fix that.

EDIT:

Specifically what’s happening is the following statement:

await RisingEdge(dut.clkdiv2)
print(get_sim_time())

Triggers twice per clock edge. (Also tested with FallingEdge, Edge, and ClockCycles)

[davidlenfesty]

I can confirm that the issue has been fixed, running a fresh build: Verilator 4.105 devel rev v4.104-81-gd21b4e3f.

The infinite loop issue I believe was related has also been fixed!

[marlonjames]

@davidlenfesty Can you check if this issue is still occuring? verilator/verilator#2644 may have fixed this.