One of my ports is not listed.

In the list of ports, I don’t see HS01 even though it exists in the IORegistry.

I’m using Clover and am in the process of converting to OpenCore. For Clover, I’m using USBInjectAll.kext but I want to switch to USBMap.kext. My Clover boot-args is this: -v dart=0 nvda_drv=1 nv_spanmodepolicy=1 keepsyms=1 debug=0x14e -lilubeta -liludbg -alcbeta -alcdbg -igfxdbg -ngfxdbg uia_exclude=HS03;HS07;HS08;HS09;HS10;HS13;HS14;USR1;USR2;SS03;SS07;SS08;SS09;SS10

HS01/SS01 are the upstream of a USB 3.0 hub on the motherboard which has two USB 3.0 connectors for four USB type A ports on the front of my computer case. All four ports currently work with both USB 2.0 and USB 3.0 devices.

I’ve attached the ioreg for all my USB controllers (chipset, Alpine Ridge, ASM1142). Should the USBMap.kext include info for the Alpine Ridge (built into the Z170X-Gaming 7 motherboard) or the ASM1142 (in a PCIe x4 slot)?

ioreg_usb.txt.zip

[corpnewt]

Hmm - I see what you mean. I found the issue in the script, but so far my attempts to fix it have broken other things. Worst-case, I’m in for another rewrite of the core logic. Best-case I can patch in support.

I’ll keep you posted. Thank you for bringing this to my attention 👍

-CorpNewt

[joevt]

Thanks for the explanation. I think I got confused again by the renumbering/renaming. Port 10 (0x0a) is in the generated Info.plist as HS09 as you say.

I guess there should be more emphasis on the fact that the names in the map will not necessarily be the same as the names in the ioreg or the UI.

I am stuck in the mindset of using the names created by USBInjectAll.kext that I’m replacing. I have therefore renamed the names in the Info.plist created by USBMap to match those names. So the reason for the mismatched names is because my USBMap that is currently in use skips the HS02 name (which I reserve for the disabled port 0x02).

Also, I was able to get the USB 3.0 hub to work by setting port 0x11 to type 3. I set port 0x01 to type 3 as well to match.