Limit amount of register information on recent GCC versions

Hi,

First, thanks for a great GDB script! I’ve been using it a lot for a year or so and I really like it. Now to the issue. On recent version of Arm toolchains, GCC 8.2, you get lots and lots of registers when doing info register. This means that the window for the “Register module” becomes huge (see [1] below). I’ve been thinking about a couple of solution for this. a) Add a context so that you could limit the amount of lines for the module, similar to other modules. b) Add some “toggle”, that can switch between only full set of register and only the core registers.

Since almost all new registers in info registers are in upper caps. I made a small change (see patch [2]) that just lists everything that is lower case. With that, the register module looks almost similar to what it used to do (see [3]).

Question: Do you want apply the patch in [2]? Want me to send a pull request or just take the patch? Want to do something different (my approach feels like a shortcut).

[1] Registers module on Arm GCC 8.2.x (not even room to show everything …)

            L2ECTLR 0x00000000                    SCTLR_EL2_S 0x00000000                    TPIDR_EL2_S 0x00000000           
          SCTLR_EL2 0x00000000                       TEEHBR_S 0x00000000                      TPIDR_EL2 0x00000000           
             TEEHBR 0x00000000                    OSLSR_EL1_S 0x0000000a                          SCR_S 0x00000000           
             SDER_S 0x00000000                    AFSR0_EL1_S 0x00000000                    AFSR1_EL1_S 0x00000000           
          OSLSR_EL1 0x0000000a                        NSACR_S 0x00000000                            SCR 0x00000000           
          AFSR0_EL1 0x00000000                      AFSR1_EL1 0x00000000                          NSACR 0x00000000           
               SDER 0x00000000                      HCR_EL2_S 0x00000000                    AFSR0_EL2_S 0x00000000           
         CPTR_EL2_S 0x00000000                     HSTR_EL2_S 0x00000000                     MDCR_EL2_S 0x00000000           
        AFSR1_EL2_S 0x00000000                        HCR_EL2 0x00000000                       MDCR_EL2 0x00000000           
           CPTR_EL2 0x00000000                      AFSR1_EL2 0x00000000                      AFSR0_EL2 0x00000000           
           HSTR_EL2 0x00000000                    AFSR0_EL3_S 0x00000000                    AFSR1_EL3_S 0x00000000           
          AFSR0_EL3 0x00000000                      AFSR1_EL3 0x00000000                      ESR_EL2_S 0x00000000           
            ESR_EL2 0x00000000                          DUMMY 0x00000000                        TTBR0_S 0x0000000000000000   
            DUMMY_S 0x00000000                          PAR_S 0x0000000000000000                  TTBR0 0x0000000000000000   
              DUMMY 0x00000000                            PAR 0x0000000000000000                  TTBR1 0x0000000000000000   
             MIDR_S 0x412fc0f1                          CTR_S 0x8444c004                        TCMTR_S 0x00000000           
            TLBTR_S 0x00000000                          TLBTR 0x00000000                    ACTLR_EL1_S 0x00000000           
            DUMMY_S 0x00000000                        TTBR1_S 0x0000000000000000              ACTLR_EL2 0x00000000           
              SCTLR 0x00c50078                      ACTLR_EL1 0x00000000                         VBAR_S 0x00000000           
               MIDR 0x412fc0f1                            CTR 0x8444c004                          TCMTR 0x00000000           
               VBAR 0x00000000                        SCTLR_S 0x00c50078                        DUMMY_S 0x00000000           
        ACTLR_EL2_S 0x00000000                        DUMMY_S 0x00000000                          DUMMY 0x00000000           
              DUMMY 0x00000000                        DUMMY_S 0x00000000                          DUMMY 0x00000000           
             PMCR_S 0x41000000                   PMCNTENSET_S 0x00000000                   PMCNTENCLR_S 0x00000000           
           PMOVSR_S 0x00000000                       PMSELR_S 0x00000000                           PMCR 0x41000000           
         PMCNTENSET 0x00000000                     PMCNTENCLR 0x00000000                         PMOVSR 0x00000000           
             PMSELR 0x00000000                      PMCCNTR_S 0x00000000                    PMXEVCNTR_S 0x00000000           
            PMCCNTR 0x00000000                      PMXEVCNTR 0x00000000                    PMUSERENR_S 0x00000000           
       PMINTENSET_S 0x00000000                   PMINTENCLR_S 0x00000000                      PMUSERENR 0x00000000           
         PMINTENSET 0x00000000                     PMINTENCLR 0x00000000                      DBGDSAR_S 0x0000000000000000   
            DBGDSAR 0x0000000000000000            TTBR0_EL1_S 0x00000000                           DFAR 0x00000000           
            MAIR0_S 0x00000000                        MAIR1_S 0x00000000                       VTCR_EL2 0x00000000           
               WFAR 0x00000000                           IFAR 0x00000000                          MAIR0 0x00000000           
              MAIR1 0x00000000                       CNTP_CTL 0x00000000                        FAR_EL2 0x00000000           
              HIFAR 0x00000000                        CNTKCTL 0x00000000                      HPFAR_EL2 0x00000000           
        TTBR1_EL1_S 0x00000000                         WFAR_S 0x00000000                         IFAR_S 0x00000000           
         CNTP_CTL_S 0x00000000                     VTCR_EL2_S 0x00000000                  CNTHCTL_EL2_S 0x00000000           
          CNTKCTL_S 0x00000000                      TTBR1_EL1 0x00000000                          TTBCR 0x00000000           
             CNTFRQ 0x03b9aca0                        HIFAR_S 0x00000000                     MAIR_EL2_S 0x00000000           
CNTHP_TVAL_EL2_S0x0 void                             HMAIR1_S 0x00000000             CNTHP_CTL_EL2_S0x0 void                 
            TCR_EL2 0x00000000                       MAIR_EL2 0x00000000                 CNTHP_TVAL_EL2 0x00000000           
             HMAIR1 0x00000000                       CNTFRQ_S 0x03b9aca0                  CNTHP_CTL_EL2 0x00000000           
        CNTHCTL_EL2 0x00000000                      TTBR0_EL1 0x00000000                      FAR_EL2_S 0x00000000           
          TCR_EL2_S 0x00000000                    HPFAR_EL2_S 0x00000000                         DFAR_S 0x00000000           
            TTBCR_S 0x00000000                       AMAIR0_S 0x00000000                     CNTV_CTL_S 0x00000000           
           AMAIR1_S 0x00000000                         AMAIR0 0x00000000                       CNTV_CTL 0x00000000           
             AMAIR1 0x00000000                    AMAIR_EL2_S 0x00000000                      HAMAIR1_S 0x00000000           
          AMAIR_EL2 0x00000000                        HAMAIR1 0x00000000                         DACR_S 0x00000000           
               CBAR 0x08000000                          PAR_S 0x0000000000000000                    PAR 0x0000000000000000   
             CBAR_S 0x08000000                           DACR 0x00000000           

[2] Patch that limit the amount of registers

From 22d5e5624f9351d64ecc1bf7157ffd231d85263a Mon Sep 17 00:00:00 2001
From: Joakim Bech <[e-mail]>
Date: Wed, 30 Jan 2019 09:49:30 +0100
Subject: [PATCH] registers: show only regular registers

Signed-off-by: Joakim Bech <[e-mail]>
---
 .gdbinit | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.gdbinit b/.gdbinit
index 39f3f5e..76e2968 100644
--- a/.gdbinit
+++ b/.gdbinit
@@ -1397,7 +1397,7 @@ class Registers(Dashboard.Module):
             # fetch register and update the table
             name = reg_info.split(None, 1)[0]
             # Exclude registers with a dot '.' or parse_and_eval() will fail
-            if '.' in name:
+            if '.' in name or name.isupper():
                 continue
             value = gdb.parse_and_eval('${}'.format(name))
             string_value = Registers.format_value(value)
-- 
2.17.1

[3] Registers module on Arm GCC 8.2.x with patch in [2] applied.

─── Registers ────────────────────────────────────────────────────────────────────────────────────────────────────────────────
                 r0 0x0e1584b0                  r1 0x00000001                  r2 0x00000000                  r3 0x00000000
                 r4 0x00000000                  r5 0x00000000                  r6 0x00000000                  r7 0x00000000
                 r8 0x00000000                  r9 0x00000000                 r10 0x00000000                 r11 0x00000000
                r12 0x00000000                  sp 0x0e183f18                  lr 0x0e11366f                  pc 0x0e101638
               cpsr 0x60000113               fpscr 0x00000000               fpsid 0x410430f0               fpexc 0x00000000
CNTHP_TVAL_EL2_S0x0 void        CNTHP_CTL_EL2_S0x0 void
─── Source ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────

[jbech-linaro]

FYI, I’ve filed a bug to the ones maintaining and putting together Arm toolchains, see here.

[cyrus-and]

460cf28c3fd898159510cc610d6c2a7c57c34247:

dashboard registers -style list defaults to show all the registers as provided by GDB. This setting is not meant to be interactively manipulated, rather it can be specified just once in a per-project .gdbinit or ~/.gdbinit.d/init files, only when needed.