RFC: overloading the >> operator for connections

While working on #25 I had some thoughts that could help make circuits more readable. It may be possible to overload the >> operator in a way that turns

vin       += r1[1], r2[1]
r2[2]     += c1[1]
c1[2]     += gnd
led1['a'] += r1[2]
led1['k'] += gnd

into

vin >> r2 >> c1 >> gnd
vin >> r1 >> led1['a']; led1['k'] >> gnd 

Some things to note:

• It needs to accept Net, Pin and Part (edit: and Bus!)
• Giving a Part will assume it “flows” into pin 1 and out pin 2 so these are equivalent:

vin >> r1[1]; r1[2] >> gnd
vin >> r1 >> gnd

There may some blocker for making this possible in the way Python works, haven’t investigated fully, but for now it would just be good to know if others agree that it would be desirable.

I don’t think overloading <<, allowing connections in the other direction, would be desirable as it would make for more confusing circuit descriptions.

[xesscorp]

I took another look at this and implemented something using the & operator to make series connections and the | operator to make parallel connections. I think this gets most of what you want except for the bus connections. You can see some examples in the section “Making Parallel and Serial Networks” here.

[kasbah]

I agree that it bares some experimentation and it would be nice to have warnings or errors on stupid behaviour. An easy one might be to allow it only on components with two pins (i.e. allow vcc >> r1, disallow vcc >> u5 and allow vcc >> u5[1]). Detecting polarized components would be a step above that.

I coming round to your point though, maybe it’s not worth the effort.

Thanks for your help. Right now, it’s just important for me to be able to bounce these ideas off of you and be able to ask stupid questions about your design choices (by the by I still have a stupid question open in #29).