xspice simulation

Thanks for this great program!

How can I perform an ngspice, xspice simulation with skidl? Here’s a simple example (buffer driven by a sinusoidal voltage source) that works using just PySpice.

#!/usr/bin/env python

from PySpice.Spice.Netlist import Circuit
from PySpice.Unit import *
from PySpice.Spice.NgSpice.Shared import NgSpiceShared

ngspice = NgSpiceShared.new_instance()
circuit = Circuit("Circuit")

circuit.SinusoidalVoltageSource(
    "vsource",
    "vin",
    circuit.gnd,
    amplitude=1.65 @ u_V,
    offset=1.65 @ u_V,
    frequency=100e6,
)
circuit.A("adc", "[vin]", "[buf_in]", model="adc")
circuit.model(
    "adc",
    "adc_bridge",
    in_low=1.6,
    in_high=1.7,
    rise_delay=1e-9,
    fall_delay=1e-9,
)
circuit.A("buf", "buf_in", "buf_out", model="buf")
circuit.model(
    "buf", "d_buffer", rise_delay=1e-9, fall_delay=1e-9, input_load=1e-12,
)
circuit.A("dac", "[buf_out]", "[vout]", "dac")
circuit.model("dac", "dac_bridge", out_low=0, out_high=3.3)
circuit.R("R", "vout", circuit.gnd, 1 @ u_kOhm)

simulator = circuit.simulator()
analysis = simulator.transient(step_time=0.1 @ u_ns, end_time=50 @ u_ns)

for (vin, vout) in zip(
    analysis["vin"].as_ndarray(), analysis["vout"].as_ndarray()
):
    print("{:.3f}\t{:.2f}".format(vin, vout))

However, I’m having trouble translating this to the equivalent skidl syntax. From the documentation/code I see that A() is used for this, but I don’t see how I can set the ports and model with this. Here’s an example of something I’ve tried, although unsurprisingly it doesn’t work.

#!/usr/bin/env python

from skidl.pyspice import *

# component declaration
vin = sinev(offset=1.65 @ u_V, amplitude=1.65 @ u_V, frequency=100e6)
adc = A("adc", "[vin]", "[buf_in]", model="adc")
adc_model = Part(
    "pyspice",
    "adc",
    "adc_bridge",
    in_low=1.6,
    in_high=1.7,
    rise_delay=1e-9,
    fall_delay=1e-9,
)
buf = A("buf", "buf_in", "buf_out", model="buf")
buf_model = Part(
    "pyspice",
    "buf",
    "d_buffer",
    rise_delay=1e-9,
    fall_delay=1e-9,
    input_load=1e-12,
)
dac = A("dac", "[buf_out]", "[vout]", "dac")
dac_model = Part("pyspice", "dac", "dac_bridge", out_low=0, out_high=3.3)
r = R(value=1 @ u_kOhm)

# component connections
vin["n"] += gnd, r["n"]
vin["p"] += adc["[vin]"]
adc["[buf_in]"] += buf["buf_in"]
buf["buf_out"] += dac["[buf_out]"]
r["p"] += dac["[vout]"]

circ = generate_netlist()
sim = circ.simulator()
waveforms = sim.transient(step_time=0.1 @ u_ns, end_time=50 @ u_ns)
time = waveforms.time
vin = waveforms[node(vin["p"])]
vout = waveforms[node(r["p"])]

print(time)
print(vin)
print(vout)

It complains starting at the adc=A(... line, which I guess is expected since the only valid attribute is model. However, I’m confused about how to actually define this model, and also how to define the ports. Thanks.

[xesscorp]

I think the A() PySPice construct became more fully-realized after I built the interface into SKiDL. I’ll need to make some modifications. Thanks for the example. That will help guide me.

[matthuszagh]

That makes a lot more sense, and now I see the benefit of the vector notation. Thanks for clearing that up. I have no further feedback at this time. Feel free to close and document.