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Decoder fails to decode a few valid AMD instructions
See original GitHub issueWrong destination register, should be xmm1 but it’s xmm0
660F78C1A5FD
wrong: extrq xmm0, 0xa5, 0xfd
correct: extrq xmm1, 0xa5, 0xfd
W1 is allowed but xed can’t decode them:
8FE9F812C3 = llwpcb rbx
8FE9F812CB = slwpcb rbx
Issue Analytics
- State:
- Created 5 years ago
- Comments:5 (3 by maintainers)
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These two instructions are a little weird, the 2nd operand is always 32-bit according to the documentation, but xed shows it as a 64-bit register:
Jup, the destination register of
extrqshould be determined bymodrm.rminstead ofmodrm.reg, as the later one must be (is forced to) zero by definition.