AES custom instruction

I’m currently working on adding a custom instruction to acceleration AES in the SMP branch.

SoC configuration :
./make.py --board=arty_a7 --cpu-count=2 --dcache-width=64 --icache-width=64 --dcache-size=8192 --dcache-ways=2 --icache-size=8192 --icache-ways=2 --aes-instruction=True --local-ip=192.168.0.159 --remote-ip=192.168.0.24 --build --load

Test :
openssl speed -elapsed -evp aes-128-cbc aes-256-cbc

SW :
type             16 bytes     64 bytes    256 bytes   1024 bytes   8192 bytes  16384 bytes
aes-256-cbc        466.55k      683.84k      787.37k      829.75k      838.31k      838.25k
aes-128-cbc        532.21k      798.63k      945.24k     1002.84k     1001.55k     1003.66k

HW AES custom instruction :
type             16 bytes     64 bytes    256 bytes   1024 bytes   8192 bytes  16384 bytes
aes-256 cbc       1781.52k     2834.07k     3323.07k     3486.72k     3465.22k     3440.10k
aes-128-cbc       1408.26k     2907.39k     3990.78k     4392.96k     4398.10k     4390.91k

So a good 4x gain 😃

Nothing is pushed yet excepter the Aes CPU Plugin : https://github.com/SpinalHDL/VexRiscv/blob/dev/src/main/scala/vexriscv/plugin/AesPlugin.scala

The foot print is light : Per CPU : 2KB ROM + 90 LUT + 75 FF

Question now is how do we want to integrate it into buildroot. Basicaly, it require a patch for libopenssl and dropbear. Question is : Is there a way (already used) to make the buildroot build depend on the SoC configuration ?

[Dolu1990]

What are the necessary changes to be made on the buildroot side

None, i mean, in general, if i do a custom instruction, the way i use it in software is by forcing its opcode in the binary. I do not rely on GCC being able to support it.

Here is an example : https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/driver/aes_custom.h#L58 defined : https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/driver/aes_custom.h#L5 defined : https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/driver/riscv.h#L205

Then, if you want to add support into the toolchaine in a “clean” way, i realy have no idea ^^

[Dolu1990]

@amr-25 Hoo i realy have no idea / opinon about this, i probably copy paster stuff found on the web ^^ Else, it is possible that at a given moment, that package was broken for RISC-V 32 bits, and didn’t compiled. A few years ago, things where much less “stable” than now ^^