finish ULX3S support
See original GitHub issueULX3S is alsmot booting, but https://github.com/enjoy-digital/linux-on-litex-vexriscv/issues/4 prevents it to go to user space. When programming the board with OpenOCD, the serial is no longer detected and then prevents using lxterm to load the linux images. When loading the ujprog, the serial is still detected correctly after bitstream is loaded.
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
(c) Copyright 2012-2019 Enjoy-Digital
(c) Copyright 2012-2015 M-Labs Ltd
BIOS built on May 7 2019 09:40:21
BIOS CRC passed (c64754ab)
--============ SoC info ================--
CPU: VexRiscv @ 50MHz
ROM: 32KB
SRAM: 4KB
L2: 8KB
MAIN-RAM: 32768KB
--========= Peripherals init ===========--
Initializing SDRAM...
SDRAM now under hardware control
Memtest OK
--========== Boot sequence =============--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LXTERM] Received firmware download request from the device.
[LXTERM] Uploading binaries/Image to 0xc0000000 (2726132 bytes)...
[LXTERM] Upload complete (15.3KB/s).
[LXTERM] Uploading binaries/rootfs.cpio to 0xc0800000 (4054528 bytes)...
[LXTERM] Upload complete (15.3KB/s).
[LXTERM] Uploading binaries/rv32.dtb to 0xc1000000 (1618 bytes)...
[LXTERM] Upload complete (14.1KB/s).
[LXTERM] Uploading emulator/emulator.bin to 0x20000000 (9128 bytes)...
[LXTERM] Upload complete (15.0KB/s).
[LXTERM] Booting the device.
[LXTERM] Done.
Executing booted program at 0x20000000
--============= Liftoff! ===============--
VexRiscv Machine Mode software built May 7 2019 10:01:09
--========== Booting Linux =============--
[ 0.000000] No DTB passed to the kernel
[ 0.000000] Linux version 5.0.9 (florent@lab) (gcc version 8.3.0 (Buildroot 2019.05-git-00938-g75f9fcd0c9)) #1 Thu May 2 17:43:30 CEST 2019
[ 0.000000] Initial ramdisk at: 0x(ptrval) (8388608 bytes)
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x00000000c0000000-0x00000000c7ffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x00000000c0000000-0x00000000c7ffffff]
[ 0.000000] Initmem setup node 0 [mem 0x00000000c0000000-0x00000000c7ffffff]
[ 0.000000] elf_hwcap is 0x1100
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 32512
[ 0.000000] Kernel command line: mem=32M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Sorting __ex_table...
[ 0.000000] Memory: 119052K/131072K available (1957K kernel code, 92K rwdata, 317K rodata, 104K init, 184K bss, 12020K reserved, 0K cma-reserved)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x114c1bade8, max_idle_ns: 440795203839 ns
[ 0.000699] sched_clock: 64 bits at 75MHz, resolution 13ns, wraps every 2199023255546ns
[ 0.005987] Console: colour dummy device 80x25
[ 0.026123] printk: console [hvc0] enabled
[ 0.030423] Calibrating delay loop (skipped), value calculated using timer frequency.. 150.00 BogoMIPS (lpj=300000)
[ 0.032373] pid_max: default: 32768 minimum: 301
[ 0.067479] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.069751] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.266660] devtmpfs: initialized
[ 0.424107] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.426071] futex hash table entries: 256 (order: -1, 3072 bytes)
[ 0.964934] clocksource: Switched to clocksource riscv_clocksource
[ 2.118148] Unpacking initramfs...
[ 8.935616] Initramfs unpacking failed: junk in compressed archive
[ 9.015373] workingset: timestamp_bits=30 max_order=15 bucket_order=0
[ 10.362975] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
[ 10.364303] io scheduler mq-deadline registered
[ 10.365359] io scheduler kyber registered
[ 17.700662] random: get_random_bytes called from init_oops_id+0x4c/0x60 with crng_init=0
[ 42.084334] OF: fdt: not creating '/sys/firmware/fdt': CRC check failed
[ 42.144834] Freeing unused kernel memory: 104K
[ 42.147410] This architecture does not have kernel memory protection.
[ 42.148354] Run /init as init process
Issue Analytics
- State:
- Created 4 years ago
- Comments:24 (17 by maintainers)
Top Results From Across the Web
ulx3s.github.io | community projects that can be used with the ...
community projects that can be used with the ULX3S FPGA ESP32 board. ... RDS Modulator RDS modulator for FPGA; This code comes complete...
Read more >ULX3S - Getting Started - Crowd Supply
Hello Everyone and that you for your support of the awesome ULX3S FPGA and ESP32 development board! Now that deliveries are finally being ......
Read more >ULX3S - Radiona
The ULX3S is a fully open source, compact, robust and affordable FPGA board ... ULX3S uses powerful Lattice Semiconductor ECP5 series FPGA chip...
Read more >ulx3s/Lobby - Gitter
So support for the Ulx3s board does not look that good. ... You can export the complete verilog (main.v) but it is incomprehensible...
Read more >Status & Support — LUNA documentation
super-speed using PIPE PHY, basic support complete; still experimental ... ULX3S, ECP5, no hardware PHY, Full-Speed/Device Mode Support.
Read more >Top Related Medium Post
No results found
Top Related StackOverflow Question
No results found
Troubleshoot Live Code
Lightrun enables developers to add logs, metrics and snapshots to live code - no restarts or redeploys required.
Start FreeTop Related Reddit Thread
No results found
Top Related Hackernoon Post
No results found
Top Related Tweet
No results found
Top Related Dev.to Post
No results found
Top Related Hashnode Post
No results found
Top GitHub Comments
So, i updated VexRiscv verilog with a specific config :
Mainly, relaxed PC calculation, and iterative mul div as currently, there is no DSP inferation in the open source flow for the ECP5.
@enjoy-digital This need to be integrated futher in the litex toolchain.
Does this seem good ?
I tried synthesis, and i get a good margin : Info: Max frequency for clock ‘$glbnet$main_soclinux_clkout0’: 61.97 MHz (PASS at 50.00 MHz)
Good, thanks.