icebreaker board: Failed to expand region (0, 0) |_> (25, 31) of 5491 ICESTORM_LCs

I am facing issue with building for Icebreaker board: python3 -m litex_boards.targets.icebreaker --build

I am using : Yosys version Yosys 0.22+82 (git sha1 2cdbb85da, clang 10.0.0-4ubuntu1 -fPIC -Os)

nextpnr-ice40 nextpnr-ice40 -- Next Generation Place and Route (Version nextpnr-0.4-28-gac17c36b)

[tcal-x]

Hi @disdi , the error message is a bit cryptic, but it’s just saying that your mapped design uses more resources than are available. In this case, you’ve used 5481 ICESTORM_LCs while the target FPGA has only 5280.

The default CPU variant does not fit on the target FPGA. While you might wonder why they don’t make the default to be something that fits for this board, I think the reasoning is that it would cause confusion if every board had a different default. So globally, the default cpu type is VexRiscv, and the default variant is “full”.

These are some recipes that should work, using smaller CPUs:

VexRiscv, “minimal”:

python3 -m litex_boards.targets.icebreaker --build --cpu-variant=minimal

or VexRiscv, “lite”:

python3 -m litex_boards.targets.icebreaker --build --cpu-variant=lite

or bit-serial SERV:

python3 -m litex_boards.targets.icebreaker --build --cpu-type=serv

[disdi]

Closing this issue for now