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Failed to analyze multiport memory with RW:1 R:1

See original GitHub issue

I am having problems compiling a multiport SRAM with 1 read-write port and 1 read-only port. I am using the following config:

word_size = 2                                                                       
num_words = 16                                                                      
                                                                                    
num_rw_ports = 1                                                                    
num_r_ports = 1                                                                     
num_w_ports = 0                                                                     
                                                                                    
tech_name = "freepdk45"                                                             
nominal_corners_only = False                                                        
process_corners = ["TT"]                                                            
supply_voltages = [1.0]                                                             
temperatures = [25]                                                                 
                                                                                    
route_supplies = False                                                              
check_lvsdrc = False                                                                
                                                                                    
analytical_delay = False                                                            
                                                                                    
purge_temp = False                                                                  
                                                                                    
output_path = "."                                                                   
output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name)

The problem is that the function parse_spice_list() is failing to parse the delay_sen1 measurement from the tmp/timing.lis file, i.e the output file from ngspice, when analysing the delays for read port 1. This is the error message in timing.lis:

Error: measure  delay_sen1  (TARG) : out of interval
.meas tran delay_sen1 trig v(clk1) val=0.5 fall=1 td=27.5n targ v(xsram_2_16_freepdk45.s_en0) val=0.5 rise=1 td=27.5n failed!

Unfortunately, the error was not caught earlier and parse_spice_list() continuously returns the string "Failed" rather than a floating-point number. This then causes the try_period() function to repeatedly fail, which in turn, forces find_min_period_one_port() into an infinite loop until a timeout occurs here.

Do you know how I can get around the problem with ngspice? Thanks!