Stuck on an issue?

Lightrun Answers was designed to reduce the constant googling that comes with debugging 3rd party libraries. It collects links to all the places you might be looking at while hunting down a tough bug.

And, if you’re still stuck at the end, we’re happy to hop on a call to see how we can help out.

Inconsistency between icePLL and iCEcube2

See original GitHub issue

When icepll is used to generate a PLL for an input frequency of 12MHz and an output of 25MHz, it gives this output:

F_PLLIN:    12.000 MHz (given)
F_PLLOUT:   25.000 MHz (requested)
F_PLLOUT:   24.000 MHz (achieved)

FEEDBACK: SIMPLE
F_PFD:   12.000 MHz
F_VCO:  768.000 MHz

DIVR:  0 (4'b0000)
DIVF: 63 (7'b0111111)
DIVQ:  5 (3'b101)

FILTER_RANGE: 1 (3'b001)

However, when iCEcube2 is given the same parameters, it generates a PLL with these parameters:

DivR: 0000 (0)
DivF: 1000010 (66)
DivQ: 101 (5)
Output frequency: 25.13MHz

It seems that iCEcube2 sets DIVF outside its documented range of [0,63], and gives a PLL configuration that more closely matches the frequency requested. Could the DIVF range given in the datasheet simply be a mistake?

I can’t verify this at the moment as I don’t have an oscilloscope.

Issue Analytics

State:
Created 6 years ago
Comments:5 (3 by maintainers)

Top GitHub Comments

1reaction

C-Eleganscommented, Jul 3, 2017

Lattice replied, the PLL DIVF range is 0-127 (At least in the simple mode)

"Hi C_Elegans,

This should be an error in TN1251. Currently in ICE40 PLL module, the DIVF is a 7bit field in HW design(in picture blow). So the range should be from 0 to 127.

Seems TN1251 need to be updated. I will raise CR to get the document updated. Regards"

0reactions

cliffordwolfcommented, Jul 3, 2017

Thanks for sorting this out! I’ve now merged your PR that sets the DIVF range to [1, 127] in simple mode.

Top Results From Across the Web

Inconsistency between icePLL and iCEcube2 #83 - GitHub

When icepll is used to generate a PLL for an input frequency of 12MHz and an output of 25MHz, it gives this output:...

iCEcube2 User Guide - Lattice Semiconductor

The iCEcube2 User Guide provides iCE FPGA designers with an overview of the software tools and the design process using iCEcube2. This document...

iCE40 sysCLOCK PLL Design and User Guide Technical Note

The iCE40 Phase-Locked Loop (PLL) provides two sets of outputs and a variety of user-synthesizable clock frequencies, along with custom phase ...

iCEcube2 User Guide - Lattice Semiconductor

Modules that have a port mismatch between instance and definition. • Both ieee.std_logic_signed and unsigned packages in VHDL.

iCEcube2 Design Software - Lattice Semiconductor

iCEcube2 design software integrates industry leading simulation and synthesis tools and is optimized for extracting more from your ultra-low density FPGA ...