Bulk connect common sub-parts of Bundles/Records

Consider the following scenario where mix-ins are used to add fields to compose a Bundle:

trait Common extends Bundle {
  val c0 = Bool()
  val c1 = Bool()
}

trait A extends Bundle with Common {
  val aa = UInt(10.W)
}

trait B extends Bundle with Common /* with Foo with Bar with ... */ {
  val bb = UInt(10.W)
}

We can now use these as I/Os for Bundles, especially for BlackBoxes:

// A BlackBox that has the following I/Os
// c0, c1, aa
class MyBBoxA extends BlackBox {
 val io = IO(Input(new A))
}

// A BlackBox that has the following I/Os
// c0, c1, bb
class MyBBoxB extends BlackBox {
 val io = IO(Output(new B))
}

The problem is that with Chisel3 semantics there is no DRY way to connect the common elements:

class MyTest extends Module {
 val io = IO(new Bundle {})
 val mod1 = Module(new MyBBoxA)
 val mod2 = Module(new MyBBoxB)
 mod1.io <> mod2.io // <-- doesn't work in Chisel3 semantics
 // Non-DRY code, want to avoid
 mod1.io.c0 <> mod2.io.c0
 mod1.io.c1 <> mod2.io.c1
}

Using composition doesn’t work since it changes the I/Os to c_c0, c_c1, bb:

class B_bad extends Bundle {
  val c = new Common
  val bb = UInt(10.W)
}

Option 1: Chisel2-style “unsafe bulk connect”. I think we want to avoid that if possible.

Option 2: some sort of “connect as parent” API. I think we can do this in a type-safe way especially if we know the common subtype:

• a.asRecordView(Common) <> b.asRecordView(Common)
• commonConnect(a, b, Common)??
• a.commonConnect(b, Common) ??

[jackkoenig]

This isn’t necessarily fixed in the way everyone wanted, but .viewAsSuperType and DataView (new in Chisel 3.5.0) more generally enables such connections in a much more elegant way than before. I’m closing this issue and suggest everyone look at the documentation: https://www.chisel-lang.org/chisel3/docs/cookbooks/dataview.html#how-do-i-connect-a-subset-of-bundle-fields.

[chrisbaldwin2]

Looks like someone beat me to the punch. Here is a better formatted version of my post

The Wildcard Bundle Assignment <*>

When using the Bundle Assignment, all elements must match between the two objects. What I would really enjoy is a wildcard assignment that allows for bundles to be split and joined, without needing to write out every signal. This helps a ton with managing a datapath where all of the signals can be wrapped in a bundle, then easily passed from one module to the next, similar to the Verilog (.*). Additionally the .* assignment could be done by a syntax like so moduel_i.io <*> _ which could assign the bundle to the variables in the current context.

Currently when assigning two bundles that don’t match, you get the following

[error] chisel3.internal.ChiselException: Connection between left (anon$2(IO io_ctrlDataOut in ControlFile)) and source (anon$2(IO in unelaborated CPUFile)) failed @.memWData: Left Record missing field (memWData).

I think that it would be better to have an explicit operator to prevent users from accidentally missing signals, but it would be nice if people wanted to “live on the edge” and use wildcards to shorten laborious assignments.