Chisel is not inferring the correct width of register

Hi,

I have experienced some issues in trying to have Chisel inferring the correct number of widths for a register.

In particular, the register should be 6-bits, but instead, a 1-bit register is defined in the Verilog.

I tried to create an example code to reproduce the issue:

class width_error extends Module{
  val io = IO(new Bundle{
    val p1 = new HMC_port()
  })

  val regTag = Reg(init = 0.U)
  val readCounter = Counter(100)

  when(readCounter.value < 50.U){
    io.p1.cmd.bits.tag := regTag
    regTag := regTag + 1.U
    readCounter.inc()
  }

}

where HMC_port is defined as follows

class HMC_port extends Bundle{

  val cmd = Decoupled(new HMCCommand)
  val wr = DecoupledIO(UInt(128.W))
  val rd = Decoupled(new HMCResponseChannel).flip

  override def cloneType = {new HMC_port().asInstanceOf[this.type ]}
}


class HMCCommand extends Bundle{
  val addr = UInt(34.W)
  val size = UInt(4.W)
  val tag = UInt(6.W)
  val cmd = UInt(4.W)

  override def cloneType = { new HMCCommand().asInstanceOf[this.type] }
}

class HMCResponseChannel extends Bundle{
  val data = UInt(128.W)
  val errstat = UInt(7.W)
  val dinv = UInt(1.W)
  val tag = UInt(6.W)

  override def cloneType = { new HMCResponseChannel().asInstanceOf[this.type ]}
}

I attach also a version of the Verilog that is produced from this code.

width_error.v.zip

[ccelio]

Thanks @lorenzoditucci, I have opened an issue #650 to help us track adding the proper documentation for this behavior.

[sbeamer]

Following up on the point made by @lorenzoditucci, how might a warning have made this less unintuitive?

Could this particular case (register declared without width and width of input to it is unknown) be detected?

Additionally, the IO assignment io.p1.cmd.bits.tag := regTag leaving 5 bits unassigned is also troubling. I don’t want to reignite the debate about warnings for unconnected IOs, but perhaps in this special case where the unconnected IOs are due to width inference, this could be also be detected.

Either way, this should be cleared up in the docs.