For this code the time from firrtl to verilg could be very slow

I wrote a code (pasted following) which the run time from firrtl to verilog was hours long. Could you help on this performance issue? The running log looks like:

mkdir: cannot create directory `target’: File exists warning: there was one deprecation warning; re-run with -deprecation for details warning: there were 49 feature warnings; re-run with -feature for details two warnings found Run starting. Expected test count is: 2 Test: [info] [0.002] Elaborating design… [info] [0.712] Done elaborating.

• elaborate [info] [0.000] Elaborating design… [info] [0.255] Done elaborating.

From this point on, the time will be very long to the end.

@jackkoenig I think you are the one who answered me at https://stackoverflow.com/questions/44849211/can-chisel-translates-firrtl-to-verilog-in-parallel-multi-cpu, Thanks. I had another trouble on sbt so I compiled my code like this way: mkdir target cp /opt/RISCV/top.cpp target scalac -d target -cp $CP Top.scala Test.scala scala -cp $CP org.scalatest.run Test # this step takes hours

The scala compiler and code runner version 2.11.8

something went wrong and the file can not be processed so I just pasted the code here, please take a look at the last class Top:

import chisel3._
import chisel3.util._

object ce_pm{
  val div = 4
  val e = 1   
  val ec= 1   
  val p = 10 // 16/div        
  val s = p*p       
  val w = s*e       

  val ext = 64      
  val extw= ext*e   

  val irp = 10 // 32/div  // this parameter matters !! 32 will cost much more time.
  val irn = irp*irp 
}

class Mux4(n: Int) extends Module {
  val io = IO(new Bundle{
    val i = Input(Vec(4,UInt(n.W)))
    val s = Input(UInt(2.W))
    val o = Output(UInt(n.W))
  })
  val mux00 = Wire(UInt(n.W))
  val mux01 = Wire(UInt(n.W))
  mux00 := Mux(io.s(0)===1.U,io.i(1),io.i(0))
  mux01 := Mux(io.s(0)===1.U,io.i(3),io.i(2))
  io.o  := Mux(io.s(1)===1.U,mux01,mux00)
}

class CEIO_TwoD_Torus extends Bundle {
  val n = Input(UInt(ce_pm.e.W))
  val s = Input(UInt(ce_pm.e.W))
  val w = Input(UInt(ce_pm.e.W))
  val e = Input(UInt(ce_pm.e.W))
}

class TwoD_TorusReg extends Module {
  val io = IO(new Bundle{
    val i = new CEIO_TwoD_Torus()
    val o = new CEIO_TwoD_Torus().flip
    val d = Input(UInt(ce_pm.e.W)) // set data
    val c = Input(Vec(4,UInt(1.W)))
  })
  val r = Reg(UInt(ce_pm.e.W),init=0.U)
  val u_mux4 = Module(new Mux4(ce_pm.e))
  u_mux4.io.i(0) := io.i.e
  u_mux4.io.i(1) := io.i.s
  u_mux4.io.i(2) := io.i.w
  u_mux4.io.i(3) := io.i.n
  u_mux4.io.s    := Cat(io.c(2),io.c(1))
  when (io.c(0) === 1.U) {
    when (io.c(3) === 0.U) {
      r := u_mux4.io.o
    } .otherwise {
      r := io.d
    }
  } 
  io.o.e := r
  io.o.s := r
  io.o.w := r
  io.o.n := r
}

class Top extends Module {    
  val io = IO(new Bundle{
    val i = Input (UInt(ce_pm.extw.W))
    val o = Output(Vec(ce_pm.p,Vec(ce_pm.p,UInt(ce_pm.e.W))))
    val c = Input (UInt(7.W))
  })
  val n  = ce_pm.irp // n matters when set 32 takes much more time
  val r_vec = (0 to n-1).map ( i=>
                (0 to n-1).map ( j=>
                  Module(new TwoD_TorusReg) // I inst many of them and then do interconnections
                )
              )
  for (i <- 0 to n-1) {
    for (j <- 0 to n-1) {
      //r_vec(i)(j).io.c := Cat(io.c(1),io.c(3),io.c(2),io.c(0)).asBits
      r_vec(i)(j).io.c(0) := io.c(1)
      r_vec(i)(j).io.c(3) := io.c(0)
      r_vec(i)(j).io.c(2) := io.c(2)
      r_vec(i)(j).io.c(1) := io.c(3)
    }
  }
  // out
  val m = ce_pm.p
  (0 to m-1).map(i=>{
    (0 to m-1).map(j=>{
      io.o(i)(j) := r_vec(i)(j).io.o.e
    })
  })
  //2-D-Torus interconnection
  (1 to n-1).map(i=>{
    (1 to n-1).map(j=>{
      r_vec(i)(j).io.i.w := r_vec(i)(j-1).io.o.e
      r_vec(i)(j).io.i.n := r_vec(i-1)(j).io.o.s
    })
  })
  (0 to n-2).map(i=>{
    (0 to n-2).map(j=>{
      r_vec(i)(j).io.i.e := r_vec(i)(j+1).io.o.w
      r_vec(i)(j).io.i.s := r_vec(i+1)(j).io.o.n
    })
  })
  (0 to n-1).map(i=>{
    r_vec(i)(0).io.i.w := r_vec(i)(n-1).io.o.e
    r_vec(0)(i).io.i.n := r_vec(n-1)(i).io.o.s
  })
}

[chick]

@apolonic If you are referring to the map statements here

  val r_vec = (0 to n-1).map ( i=>
                (0 to n-1).map ( j=>
                  Module(new TwoD_TorusReg)
                )
              )

You cannot use foreach in this case, so map is ok, but the simplest way of getting your 2d data structure is

  val r_vec = Array.fill(n, n)(Module(new TwoD_TorusReg))

Checkout Creating collections from scratch for a handy cheatsheet. I like to use tabulate when the elements I am creating depend on their indices. In the case at hand though, fill is the proper way.

[ducky64]

This has been inactive for a while, if it’s still an issue feel free to reopen.