Modifying the name of the module that comes from Chisel Library.

Type of issue: other enhancement

Impact: API addition (no impact on existing code)

Development Phase: proposal

What is the current behavior?

If I create a Module which from Chisel Library, for example, Queue, there will be a verilog module named Queue. In the meantime, if another person also creates a Queue, my Queue will conflict with his because two modules have the same name. But I can’t modify the name of Queue dynamically.

What is the expected behavior?

I want to generate modules of the Chisel Library with custom names. Maybe a better desiredName method will work. However, I can only do it like this:

class MyQueue[T <: Data](gen: T, entries: Int) extends Queue(gen, entries)
val mq = Module(new MyQueue(g, e))

Please tell us about your environment: - version: 3.2-SNAPSHOT - OS: Ubuntu 16.04

What is the use case for changing the behavior? Nothing.

[jackkoenig]

Note that we do not currently support -moduleNamePrefix, I am proposing adding such support to Chisel3/FIRRTL, most likely as a FIRRTL transform.

[jackkoenig]

Chisel 2 provided a -moduleNamePrefix to add a prefix to each Module name. This is one approach to “namespacing” that could solve this issue. For example, you could provide -moduleNamePrefix StarBrilliance then you would have names like StarBrillianceQueue. Does this sound like a satisfactory solution @starbrilliance?