strange problem when i use when and otherwise

strange problem happened that when condition is fulfilled, expression 1 executed but expression 2 also executed.

when(condition) {
   expression 1
} .otherwise{
   expression 2
}

[chick]

This is an extra refinement of the code above. Assuming in fact what is going on here is some 2 dimensional mapping of inputs into a register array, you should take advantage of the ability to represent the problem in a 2D fashion in your code. I think it makes this easier to read and easier to reason about. Here is an example of the same Module but written in 2D model.

class PadProblem2D(pad: Int, width: Int, height: Int, w: Int) extends Module {
  val in_pad_width  = 2*pad + width
  val in_pad_height = 2*pad + height

  val io = IO(new Bundle {
    val inputs = Vec(height, Vec(width, Input(UInt(w.W))))
  })

  val inputs_pad    = Seq.fill(in_pad_width, in_pad_height){ Reg(UInt(w.W)) }

  // put zeros around edges
  // first do bottom and top row
  inputs_pad.head.foreach { cell => cell := 0.U }
  inputs_pad.last.foreach { cell => cell := 0.U }
  // do first and last column
  inputs_pad.indices.foreach { index =>
    inputs_pad(index).head := 0.U
    inputs_pad(index).last := 0.U
  }

  // wire the interior of the padded registers to the inputs
  for (row <- 0 until height) {
    for (col <- 0  until width) {
      inputs_pad(row + 1)(col + 1) := io.inputs(row)(col)
    }
  }
}

Note:

• I have made the inputs a Vec of Vecs (2D)
• I have used Seq.fill in a 2D context to create the register array
• I initialize the outside of the register array using scala seq methods
• The interior of the register array is more neatly described using 2d indexing
• The generated firrtl is not any shorter but the final names are more readable as 2D indices
• You could also rely on Chisel’s last connect semantics to initialize them all to zero
  • your later connects would override the zeros in the interior of the register array
  • note the RegInit instead of Reg
  • you could then remove the `//put zeroes around the edges`` code section

  val inputs_pad    = Seq.fill(in_pad_width, in_pad_height){ RegInit(0.U(w.W)) }

[chick]

Here’s my best guess at what you are trying to do, in particular I am guessing at the structure of your inputs. This should still provides some help even if I got this assumption wrong

class PadProblem(pad: Int, width: Int, height: Int, w: Int) extends Module {
  val in_pad_width  = 2*pad + width
  val in_pad_height = 2*pad + height
  val padSize = in_pad_width * in_pad_height

  val io = IO(new Bundle {
    val inputs = Vec(width * height, Input(UInt(w.W)))
  })

  val inputs_pad    = Seq.fill(in_pad_width * in_pad_height){ Reg(UInt(w.W)) }

  for (row <- 0 until in_pad_height) {
    for (col <- 0  until in_pad_width) {
      val idx = (row * in_pad_width) + col

      if(row == 0 || col == 0 || row == in_pad_height - 1 || col == in_pad_width - 1) {
        println(s"padding at ($row,$col) idx $idx")
        inputs_pad(idx) := 0.U
      }
      else {
        val idx_in = ((row-1) * width) + (col - 1)
        println(s"connecting ($row, $col) $idx from $idx_in")
        inputs_pad(idx) := io.inputs(idx_in)
      }
    }
  }
}

Notes

• It seems like you creating a 2d set of registers that are mapped to a 2d set of inputs
• The set of registers are padded around the outside
  • The pad registers are initialized to 0.U
• Unless you need to use hardware addressing of a structure you do not need to create a Vec
  • Instead just keep track of them using Scala structures
• You do not need when, instead you need to conditionally construct hardware
  • That means use scala if
  • println helps show how it initializes during construction
• The above elaborates correctly given my assumptions
• Let me if this helps