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adding vec initialisation in chisel3 cheat sheet

See original GitHub issue

Type of issue: documentation

Impact: no functional change

Development Phase: request

Other information Is it possible to add Vec initialization in the cheat sheet for chisel 3 ? I don’t know exactly where to find the source of this document (cheat sheet).

For example, here a vec initialization of a register file of 31 UInt registers of 32bits width.

val regfile = RegInit(VecInit(Seq.fill(31)(0.U(32.W))))

The cheat sheet I’m using is the version 0.5 here.

Issue Analytics

State:
Created 4 years ago
Comments:6 (6 by maintainers)

Top GitHub Comments

1reaction

ducky64commented, Jun 17, 2019

Actually, we recently open-sourced the cheatsheet: https://github.com/freechipsproject/chisel-cheatsheet

A cleaning pass (including adding VecInit) is on my to-do list (Soon™), but we also do accept pull requests.

0reactions

Martonicommented, Jun 17, 2019

Issue added to right repository here

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