Type after shift in IntelliJ

Maybe this is just a bug in IntelliJ, but let’s see if someone has an idea.

Type of issue: bug report

Following code

  val a = 1.U << 1
  val b = 3.U
  println(a, b)

  // IntelliJ editor complains on 'a': Type mismatch, expected UInt, actual: Bits
  when(b >= a) {
    io.data := 1.U
  }

displays an error in the IntelliJ editor (a is marked in the when expression). The editor thinks that the shift operation in the first line results in Bits and not a UInt.

However, the code compiles correctly with IntelliJ and also with sbt from the terminal.

What, in the Chisel type system, is confusing the IntelliJ editor here?

Please tell us about your environment: -version 3.1.8

• IntelliJ latest on Mac (just updated)

The example is available here: https://github.com/schoeberl/chisel-playground/blob/master/src/main/scala/issues/Shift.scala

[ducky64]

Implicit conversions: there’s been some discussion on making the separation of Bits and UInt better, so it might not be safe to have Bits automatically cast to UInt.

I think a typeclass solution on Bits makes sense, and I remember hearing that having macros change the return type was discouraged and may go away in a future Scala version. One caveat here is that it needs to not bleed into the user facing API (this is what prevented a typeclass approach to static-typed literals - it would have required something like MyBundle extends Bundle with StaticLiteral[MyBundle]), but since this only affects the Bits hierarchy (which we don’t expect users to extend), that shouldn’t be a problem

[schoeberl]

BTW, the same issue is true with Eclipse 😦

And another example:

  val blkReg = Reg(UInt(1.W))

  cntReg := cntReg + 1.U
  when(cntReg === CNT_MAX) {
    cntReg := 0.U
    blkReg := ~blkReg
  }
  io.led := blkReg
}

on blkReg := ~blkReg it complains with a type mismatch.