Add Option to Disable Div(a, a) -> 1 Fold

Checklist

• Did you specify the current behavior?
• Did you specify the expected behavior?
• Did you provide a code example showing the problem?
• Did you describe your environment?
• Did you specify relevant external information?

What is the current behavior?

The following FIRRTL program

circuit top_mod :
  module top_mod :
    input inp_1: UInt<14>
    output tmp4: UInt<14>
    tmp4 <= div(inp_1, inp_1)

Compiled with firrtl-1.4.0 generates the following Verilog

module top_mod(
  input  [13:0] inp_1,
  output [13:0] tmp4
);
  assign tmp4 = 14'h1;
endmodule

What is the expected behavior?

Expected the following Verilog

module top_mod(
  input  [13:0] inp_1,
  output [13:0] tmp4
);
  assign tmp4 = inp_1 / inp_1;
endmodule

Formal tool Yosys (Yosys 0.9+3755 (git sha1 442d19f6, clang 11.0.0 -fPIC -Os)) reports mismatch between current and expected result:

ERROR: Found 13 unproven $equiv cells in 'equiv_status -assert'.

Steps to Reproduce

./firrtl-1.4.0 -i top_mod.fir

Your environment

Linux linux-sydi 5.9.14-1-default #1 SMP Sat Dec 12 06:57:32 UTC 2020 (c648a46) x86_64 x86_64 x86_64 GNU/Linux

External Information

https://twitter.com/wavedrom/status/1342932252531945472

https://github.com/llvm/circt/issues/363

[jackkoenig]

Looking at the CIRCT issue, it looks like we’re all on the same page that this is a desirable optimization despite it being a LEC failure. It would be nice if we had a way of expressing LEC-failing optimizations in a way that we could waive such differences but still check the rest of the design.

[drom]

Perhaps the simplest solution would be to provide an option to disable LEC-violating optimizations.

After running my FIRRTL fuzzer, I have found only one optimization that breaks Yosys LEC beyond repair, so far. It would help me a lot having an option to disable A / A -> 1.