Module with multiple memories have no readmem statements

Checklist

• Did you specify the current behavior?
• Did you specify the expected behavior?
• Did you provide a code example showing the problem?
• Did you describe your environment?
• Did you specify relevant external information?

What is the current behavior?

I noticed that having multiple memory objects, the readmem statements are not generated for neither memory.

Just commenting out the mem2 and loadStorePort2 objects, mem gets it’s readmemh.

Here is a sample code I’m using:

package utils

import chisel3._
import chisel3.util.log2Ceil
import chisel3.util.experimental.loadMemoryFromFileInline
import chisel3.experimental.{annotate, ChiselAnnotation}
import firrtl.annotations.MemorySynthInit

class MultiMem extends Module {
  val io = IO(new Bundle() {
    val loadStorePort = Flipped(new MemoryPort(32, 32, true))
    val loadStorePort2 = Flipped(new MemoryPort(32, 32, true))
  })
  annotate(new ChiselAnnotation {
    override def toFirrtl =
      MemorySynthInit
  })
  val mem1 =
    Module(
      new DualPortRAM(
        sizeBytes = 32 * 1024,
        bitWidth = 32,
        memoryFile = "sample.hex"
      )
    )
  mem1.io.loadStorePort <> io.loadStorePort

  val mem2 =
    Module(
      new DualPortRAM(
        sizeBytes = 32 * 1024,
        bitWidth = 32,
        memoryFile = "sample.hex"
      )
    )
  mem2.io.loadStorePort <> io.loadStorePort2
}

class MemoryPort(val bitWidth: Int, val words: Int, val rw: Boolean)
    extends Bundle {
  val addr = Output(UInt(log2Ceil(words).W))
  val readData = Input(UInt(bitWidth.W))

  val writeEnable = if (rw) Some(Output(Bool())) else None
  val writeData = if (rw) Some(Output(UInt(bitWidth.W))) else None
}

class DualPortRAM(
    sizeBytes: Int = 1,
    bitWidth: Int = 32,
    memoryFile: String = ""
) extends Module {
  val words = sizeBytes / bitWidth
  val io = IO(new Bundle() {
    val loadStorePort = Flipped(new MemoryPort(bitWidth, words, true))
  })
  
  val mem = SyncReadMem(words, UInt(bitWidth.W))

  if (memoryFile.trim().nonEmpty) {
    println(s"  Load memory file: " + memoryFile)
    loadMemoryFromFileInline(mem, memoryFile)
  }

  io.loadStorePort.readData := mem.read(io.loadStorePort.addr)

  when(io.loadStorePort.writeEnable.get) {
    mem.write(io.loadStorePort.addr, io.loadStorePort.writeData.get)
  }
}

object MultiMem extends App {
  (new chisel3.stage.ChiselStage).emitVerilog(
    new MultiMem(),
    Array("-X", "verilog") ++ args
  )
}

Am I doing something wrong in my code or really is there is a problem in generation? Is there a real case use for this?

What is the expected behavior?

Both memories have their readmem statements.

Steps to Reproduce

Code below

Your environment

Chisel and Firrtl SNAPSHOT.

External Information

[carlosedp]

I tested this out with Chisel3 3.5-SNAPSHOT as of 20/07/2021 and saw that if the memory instances have different width or size and different hex files, both instances are correctly generated in the output Verilog.

But I still see some problems with some cases:

• If I have both memory instances with same width, size and hex file, it gets deduplicated and only one module is generated in the output.
• If I have the memories with same width and size but different hex files, I get the error below:

[error] (run-main-e) firrtl.FirrtlUserException: At least one memory annotation did not deduplicate: got non-local annotation $a from [[DedupAnnotationsTransform]]
[error] firrtl.FirrtlUserException: At least one memory annotation did not deduplicate: got non-local annotation $a from [[DedupAnnotationsTransform]]
[error] stack trace is suppressed; run last Compile / bgRun for the full output
[error] Nonzero exit code: 1
[error] (Compile / run) Nonzero exit code: 1
[error] Total time: 2 s, completed Jul 20, 2021, 3:18:23 PM

My main use-case for this feature is to have reusable memory modules that could be customized in the generation, like one 32k memory A that is initialized by A.hex and a second 32k memory B that is initialized by B.hex.

Cc. @jared-barocsi

[jackkoenig]

Fixed by https://github.com/chipsalliance/firrtl/pull/2286, to be released in FIRRTL 1.4.4 (Chisel 3.4.4)