crash 2651

Checklist

• Did you specify the current behavior?
• Did you specify the expected behavior?
• Did you provide a code example showing the problem?
• Did you describe your environment?
• Did you specify relevant external information?

What is the current behavior?

The following FIRRTL program.

; seed: 2651
circuit top_mod :
  module top_mod :
    input clock: Clock
    wire _tmp18: SInt<2>
    wire _tmp27: SInt<24>
    _tmp18 <= rem(asSInt(UInt<21>(932719)), SInt<2>("b-10"))
    _tmp27 <= add(_tmp18, SInt<23>("o-15035672"))
    assert(clock, xorr(UInt<16>("h4045")), xorr(_tmp27), "assert31")

Running with firrtl-1.5.0-SNAPSHOT crashes with the following error:

firrtl
Exception in thread "main" firrtl.FirrtlInternalException: Internal Error! trying to emit unsupported operator: UnknownType
Please file an issue at https://github.com/ucb-bar/firrtl/issues
        at firrtl.Utils$.error(Utils.scala:491)
        at firrtl.Utils$.throwInternalError(Utils.scala:164)
        at firrtl.VerilogEmitter.emitCol(VerilogEmitter.scala:205)
        at firrtl.VerilogEmitter.$anonfun$emitCol$2(VerilogEmitter.scala:197)
        at firrtl.VerilogEmitter.$anonfun$emitCol$2$adapted(VerilogEmitter.scala:196)
        at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
        at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
        at scala.collection.immutable.List.foldLeft(List.scala:79)
        at firrtl.VerilogEmitter.emitCol(VerilogEmitter.scala:196)
        at firrtl.VerilogEmitter.$anonfun$emitCol$2(VerilogEmitter.scala:197)
        at firrtl.VerilogEmitter.$anonfun$emitCol$2$adapted(VerilogEmitter.scala:196)
        at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
        at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
        at scala.collection.immutable.List.foldLeft(List.scala:79)
        at firrtl.VerilogEmitter.emitCol(VerilogEmitter.scala:196)
        at firrtl.VerilogEmitter.emit(VerilogEmitter.scala:124)
        at firrtl.VerilogEmitter$VerilogRender.$anonfun$emit_streams$6(VerilogEmitter.scala:1106)
        at firrtl.VerilogEmitter$VerilogRender.$anonfun$emit_streams$6$adapted(VerilogEmitter.scala:1106)
        at scala.collection.IterableOnceOps.foreach(IterableOnce.scala:563)
        at scala.collection.IterableOnceOps.foreach$(IterableOnce.scala:561)
        at scala.collection.AbstractIterable.foreach(Iterable.scala:919)
        at firrtl.VerilogEmitter$VerilogRender.emit_streams(VerilogEmitter.scala:1106)
        at firrtl.VerilogEmitter$VerilogRender.emit_verilog(VerilogEmitter.scala:1226)
        at firrtl.VerilogEmitter.$anonfun$emit$2(VerilogEmitter.scala:1267)
        at scala.collection.immutable.List.foreach(List.scala:333)
        at firrtl.VerilogEmitter.emit(VerilogEmitter.scala:1261)
        at firrtl.VerilogEmitter.$anonfun$execute$2(VerilogEmitter.scala:1279)
        at scala.collection.immutable.List.flatMap(List.scala:293)
        at scala.collection.immutable.List.flatMap(List.scala:79)
        at firrtl.VerilogEmitter.execute(VerilogEmitter.scala:1276)
        at firrtl.SystemVerilogEmitter.execute(SystemVerilogEmitter.scala:29)
        at firrtl.Transform.transform(Compiler.scala:319)
        at firrtl.Transform.transform$(Compiler.scala:319)
        at firrtl.SeqTransform.transform(Compiler.scala:401)
        at firrtl.stage.transforms.ExpandPrepares.execute(ExpandPrepares.scala:19)
        at firrtl.Transform.transform(Compiler.scala:319)
        at firrtl.Transform.transform$(Compiler.scala:319)
        at firrtl.stage.transforms.ExpandPrepares.transform(ExpandPrepares.scala:7)
        at firrtl.stage.transforms.CatchCustomTransformExceptions.execute(CatchCustomTransformExceptions.scala:10)
        at firrtl.Transform.transform(Compiler.scala:319)
        at firrtl.Transform.transform$(Compiler.scala:319)
        at firrtl.stage.transforms.CatchCustomTransformExceptions.transform(CatchCustomTransformExceptions.scala:7)
        at firrtl.stage.transforms.UpdateAnnotations.$anonfun$internalTransform$1(UpdateAnnotations.scala:22)
        at firrtl.Utils$.time(Utils.scala:170)
        at firrtl.Transform$.runTransform(Compiler.scala:217)
        at firrtl.stage.transforms.UpdateAnnotations.internalTransform(UpdateAnnotations.scala:22)
        at firrtl.stage.transforms.UpdateAnnotations.internalTransform(UpdateAnnotations.scala:8)
        at firrtl.options.Translator.transform(Phase.scala:248)
        at firrtl.options.Translator.transform$(Phase.scala:248)
        at firrtl.stage.transforms.UpdateAnnotations.transform(UpdateAnnotations.scala:8)
        at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:278)
        at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
        at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
        at scala.collection.immutable.List.foldLeft(List.scala:79)
        at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
        at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
        at firrtl.stage.TransformManager.transform(TransformManager.scala:14)
        at firrtl.stage.phases.Compiler.$anonfun$internalTransform$6(Compiler.scala:120)
        at firrtl.Utils$.time(Utils.scala:170)
        at firrtl.stage.phases.Compiler.f$1(Compiler.scala:120)
        at firrtl.stage.phases.Compiler.$anonfun$internalTransform$8(Compiler.scala:125)
        at scala.collection.immutable.List.map(List.scala:246)
        at scala.collection.immutable.List.map(List.scala:79)
        at firrtl.stage.phases.Compiler.internalTransform(Compiler.scala:125)
        at firrtl.stage.phases.Compiler.internalTransform(Compiler.scala:45)
        at firrtl.options.Translator.transform(Phase.scala:248)
        at firrtl.options.Translator.transform$(Phase.scala:248)
        at firrtl.stage.phases.Compiler.transform(Compiler.scala:45)
        at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:30)
        at firrtl.stage.phases.CatchExceptions.transform(CatchExceptions.scala:17)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
        at firrtl.options.Translator.transform(Phase.scala:248)
        at firrtl.options.Translator.transform$(Phase.scala:248)
        at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
        at firrtl.options.DependencyManager.$anonfun$transform$3(DependencyManager.scala:278)
        at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
        at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
        at scala.collection.immutable.List.foldLeft(List.scala:79)
        at firrtl.options.DependencyManager.transform(DependencyManager.scala:269)
        at firrtl.options.DependencyManager.transform$(DependencyManager.scala:255)
        at firrtl.options.PhaseManager.transform(DependencyManager.scala:436)
        at firrtl.stage.FirrtlStage.run(FirrtlStage.scala:38)
        at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
        at firrtl.options.Stage$$anon$1.transform(Stage.scala:43)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:38)
        at firrtl.options.phases.DeletedWrapper.internalTransform(DeletedWrapper.scala:15)
        at firrtl.options.Translator.transform(Phase.scala:248)
        at firrtl.options.Translator.transform$(Phase.scala:248)
        at firrtl.options.phases.DeletedWrapper.transform(DeletedWrapper.scala:15)
        at firrtl.options.Stage.$anonfun$transform$5(Stage.scala:47)
        at scala.collection.LinearSeqOps.foldLeft(LinearSeq.scala:169)
        at scala.collection.LinearSeqOps.foldLeft$(LinearSeq.scala:165)
        at scala.collection.immutable.List.foldLeft(List.scala:79)
        at firrtl.options.Stage.$anonfun$transform$3(Stage.scala:47)
        at logger.Logger$.$anonfun$makeScope$2(Logger.scala:166)
        at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
        at logger.Logger$.makeScope(Logger.scala:164)
        at firrtl.options.Stage.transform(Stage.scala:47)
        at firrtl.options.Stage.execute(Stage.scala:58)
        at firrtl.options.StageMain.main(Stage.scala:71)
        at firrtl.stage.FirrtlMain.main(FirrtlStage.scala)
        at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
        at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
        at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
        at java.base/java.lang.reflect.Method.invoke(Method.java:566)
        at coursier.bootstrap.launcher.a.a(Unknown Source)
        at coursier.bootstrap.launcher.Launcher.main(Unknown Source)

What is the expected behavior?

Not to crash. Give a more informative Error or Warning or just work.

Steps to Reproduce

./firrtl-1.5.0-SNAPSHOT -i top_mod.fir

Your environment

Linux linux-sydi 5.11.4-1-default #1 SMP Mon Mar 8 05:16:55 UTC 2021 (be77cd2) x86_64 x86_64 x86_64 GNU/Linux

• Verilator version: Verilator 4.109 devel rev v4.108-38-g36eb952b

External Information

[seldridge]

You are asking: if it is OK for FIRRTL to crash when legal FIRRTL program is compiled? I don’t know. It is the question to FIRRTL gurus. @jackkoenig @azidar @seldridge

😂

You’re both right in different ways. This is clearly a bug. If we crash on any legal input FIRRTL, it’s bad.

If the code is legal FIRRTL that is impossible for Chisel to ever emit, it’s less worrying, lower priority, etc. However, I’m pretty sure somebody could generate this code in a transform and cause problems. The FIRRTL compiler should be able to stand alone.

If the bug is what I think here (a transform can produce UnknownType, but that transform does not list InferTypes as something it invalidates), then the best way to prevent this in the future would be for me or somebody to revive: https://github.com/chipsalliance/firrtl/tree/check-transforms. That automatically checks transforms to see if they violate any invalidations. In the past, problematic examples fall out quickly from that. As a quick hack, dumping the circuit (with type information) inside each transform in the Verilog emitter may provide some clues as to where this is going wrong.

[itviewer]

@drom Sorry, it seems that the problem is not caused by SIntLiteral. Let me see if I can figure out what the problem is.