Registers which have dangling input generates incorrect verilog

Ticket migrated from:

https://github.com/ucb-bar/chisel3/issues/621

Correct behavior for register declaration in chisel is for register to keep the previous value even if the input is dangling. Current verilog generation does not have that behavior, instead the register is taken out to be a wire, so in synthesis, the wire is always floating instead of able to keep the initial random value.

Relevent portion from the chisel thread: Firrtl:

circuit RandTop :
  module RandTop :
    input clock : Clock
    input reset : UInt<1>
    output io : {out : UInt<32>}

    clock is invalid
    reset is invalid
    io is invalid
    reg rand : UInt<32>, clock @[Rand.scala 8:17]
    io.out <= rand @[Rand.scala 9:10]

Current Verilog:

module RandTop(
  input         clock,
  input         reset,
  output [31:0] io_out
);
  reg [31:0] rand$;
  reg [31:0] _GEN_0;
  assign io_out = rand$;
`ifdef RANDOMIZE
  integer initvar;
  initial begin
    `ifndef verilator
      #0.002 begin end
    `endif
  `ifdef RANDOMIZE_REG_INIT
  _GEN_0 = {1{$random}};
  rand$ = _GEN_0[31:0];
  `endif
  end
`endif
endmodule

Should have:

module RandTop(
  input         clock,
  input         reset,
  output [31:0] io_out
);
  reg [31:0] rand$;
  reg [31:0] _GEN_0;
  assign io_out = rand$;
`ifdef RANDOMIZE
  integer initvar;
  initial begin
    `ifndef verilator
      #0.002 begin end
    `endif
  `ifdef RANDOMIZE_REG_INIT
  _GEN_0 = {1{$random}};
  rand$ = _GEN_0[31:0];
  `endif
  end
`endif
  always @(posedge clock) begin
    rand$ <= rand$;
    // or perhaps
    rand$ <= _GEN_0;
  end
endmodule

[aswaterman]

Registers should definitely still be randomized, as this is a fairly realistic model of the hardware.

There is a legitimate question as to whether disconnected wires should be, though. @jchang0 raises a good point that synthesis is more conservative than our simulation model by driving floating wires to 0. We should seriously consider following suit. Note, this will also improve simulation performance, possibly dramatically, as we can then constant-propagate code dependent on disconnected wires.

[aswaterman]

Similarly, constant-propagating registers that are not reset and never assigned makes sense.