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Verify that mux tree generation results in good QoR

See original GitHub issue

Right now we’re generating code like addr == 3 ? elt3 : (addr == 2 ? elt2 : (addr == 1 ? elt1 : elt0)). Verify that Design Compiler does a good job with that, as compared to balanced trees (addr[1] ? (addr[0] ? elt3 : elt2) : (addr[0] ? elt1 : elt0)) and explicit decoding ((addr == 3 ? elt3 : 0) | (addr == 2 ? elt2 : 0) | (addr == 1 ? elt1 : 0) | (addr == 0 ? elt0 : 0)).

Issue Analytics

State:
Created 6 years ago
Comments:16 (14 by maintainers)

Top GitHub Comments

1reaction

aswatermancommented, Apr 14, 2017

It would be genuinely surprising if they do anything smarter than the reflective pattern I mentioned. When there’s more time, I’ll verify that; but since DC is doing a good job already, this is a decidedly lower priority issue than I thought.

1reaction

aswatermancommented, Apr 13, 2017

I think it varies from issue to issue, and relying on synthesis tools is the right approach for some things (e.g., datapath synthesis with redundant forms, like computing a*b+c).

Agreed that all Chisel utils should be audited for QoR.

Not sure about the mux vs. case matter; I’m going to look into it.

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