shift right does not complain about shift size greater than width

The firrtl spec 7.12

The shift right operation truncates the least significant n bits from e. n must be non-negative and strictly less than the bit width of e.

The following code, run with n = 8, 9, 10

class BrokenShifter(n: Int) extends Module {
  val io = IO(new Bundle {
    val i = Input(FixedPoint(8.W, 4.BP))
    val o = Output(FixedPoint(8.W, 4.BP))
    val si = Input(SInt(8.W))
    val so = Output(SInt(8.W))
  })
  io.o := io.i >> n
  io.so := io.si >> n
}

generates the following firrtl, which is processed without complaint.

circuit BrokenShifter : 
  module BrokenShifter : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip i : Fixed<8><<4>>, o : Fixed<8><<4>>, flip si : SInt<8>, so : SInt<8>}
    
    io is invalid
    io is invalid
    node _T_10 = shr(io.i, 9) @[FixedPointSpec.scala 135:16]
    io.o <= _T_10 @[FixedPointSpec.scala 135:8]
    node _T_11 = shr(io.si, 9) @[FixedPointSpec.scala 136:18]
    io.so <= _T_11 @[FixedPointSpec.scala 136:9]
    

[chick]

ok, seems like I should just update the firrtl spec

[azidar]

Resolution: need update spec.