Wiring pass for bundle produces invalid access to non-reference

@azidar @seldridge

Kindly consider the unit test at the bottom of this report.

The use case is to wire a bundle from module A to module B through parent module T.

I use the off-the-shelf WiringTransform. For this example, I reduced to the wiring pass itself.

Is this feature supported?

Error message

firrtl.passes.CheckChirrtl$InvalidAccessException: : [module T] Invalid access to non-reference.
firrtl.passes.CheckChirrtl$InvalidAccessException: : [module T] Invalid access to non-reference.

Occurs for expression a.auto_0, RHS of connect stmt in module T.

Annotated output of wiring pass

circuit T :
  module A :
    input clock : Clock
    input reset : UInt<1>
    output auto : { [..] }
    output auto_0 : { [..] } // NEWLY created only
    auto_0 <= auto

  module B :
    input clock : Clock
    input reset : UInt<1>
    input pin : { [..] } // PIN added
 
  module T :
    input clock : Clock
    input reset : UInt<1>
    inst a of A
    inst b of B
    wire auto : { [..] }
    auto <= a.auto_0 // <--- **ERROR**
    b.pin <= auto

Unit test

 "Wire a bundle from A to B" in {
    val firrtl = """
circuit T :
  module A :
    input clock : Clock
    input reset : UInt<1>
    output auto : { [..] }

  module B :
    input clock : Clock
    input reset : UInt<1>

  module T :
    input clock : Clock
    input reset : UInt<1>
    inst a of A
    inst b of B
      """

    val wi = new WiringInfo(
      source = "A",
      comp = "auto",
      sinks = Set("B"),
      pin = "pin",
      top = "T"
    )

    val passes = Seq( new Wiring(Seq(wi)) )

    val c = passes.foldLeft(Parser.parse(firrtl)) {
      (c: Circuit, p: Pass) => p.run(c)
    }

    //println(c.serialize)

    val compiler = new HighFirrtlCompiler // this will trigger 
    val writer = new java.io.StringWriter
    compiler.compile(CircuitState(c, ChirrtlForm), writer)
  }

[edcote]

Thanks for replies. I will follow up before EOD.

On Tue, Jan 9, 2018, 11:28 AM Adam Izraelevitz [e-mail] wrote:

The plan of record is to remove Chirrtl entirely, and its something I’m currently working on. But yes, if you need to convert from WIR to IR, @seldridge https://github.com/seldridge’s solution works. We should also have a WorkingIRToIR pass, so if somebody wants to PR that, it would readily be accepted.

There is not a mailing list, though there has been some in-person discussions about starting one. We just created a public gitter channel, so for now feel free to ask questions there! It was specifically created to encourage collaboration with non-Berkeley folks.

@edcote https://github.com/edcote , if @seldridge https://github.com/seldridge’s solution fixes your bug, feel free to close the issue.

— You are receiving this because you were mentioned.

Reply to this email directly, view it on GitHub https://github.com/freechipsproject/firrtl/issues/726#issuecomment-356388462, or mute the thread https://github.com/notifications/unsubscribe-auth/AZIj67lL25yh5FNUUit5Xe2lQqeY5FR9ks5tI73tgaJpZM4RYBd8 .

[edcote]

Thanks. Sorry for non followup. Was waiting for annotation changes to go in before trying again

On Fri, Mar 9, 2018, 9:37 AM Adam Izraelevitz [e-mail] wrote:

@edcote https://github.com/edcote, I’m going to assume @seldridge https://github.com/seldridge answered the question and close the issue. Please reopen it if I am mistaken.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub https://github.com/freechipsproject/firrtl/issues/726#issuecomment-371885121, or mute the thread https://github.com/notifications/unsubscribe-auth/AZIj60cnhd_pCmVGkfQh7_NkyOZWyhacks5tcr3IgaJpZM4RYBd8 .