Automatically deduction of TOPLEVEL_LANG doesn't work

Hi. It is my first time using cocotb with Xcelium (always GHDL or iverilog). Has far I understand it must work, but fail.

• the cocotb version used: 1.5.2
• the operating system and version: Centos7, 64 bits
• the simulator and version: Xcelium (19.09), 64 bits
• the Python version, and where it’s coming from: 3.7.0 (pyenv)

Log:

/.../.pyenv/versions/3.7.0/lib/python3.7/site-packages/cocotb/share/makefiles/simulators/Makefile.xcelium:103: *** "A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=".  Stop.

Makefile

#TOPLEVEL_LANG=verilog

VERILOG_SOURCES += ../vlog/counter.v
TOPLEVEL = counter
MODULE = counter

include $(shell cocotb-config --makefiles)/Makefile.sim

clean::
	@rm -fr __pycache__ *.vcd *.xml

I need to uncomment TOPLEVEL_LANG. to avoid this.

[ktbarrett]

So I added a print at line 112 above and it started working. Seems like it’s a gmake bug… Also tried with other simulators and see the same problem.

[rodrigomelo9]

But I have only Verilog files… one Verilog file to be more precise. I wrote also mi Makefile in the issue description:

#TOPLEVEL_LANG=verilog

VERILOG_SOURCES += ../vlog/counter.v
TOPLEVEL = counter
MODULE = counter

include $(shell cocotb-config --makefiles)/Makefile.sim

clean::
	@rm -fr __pycache__ *.vcd *.xml

I didn’t set VHDL_SOURCES.