Incorrect AMD XOP definitions

Some of the AMD XOP instructions seem to have incorrect operand definitions. BLCFILL for example uses the GPRy_N() register-class, which is declared as:

xed_reg_enum_t GPRy_N()::
EASZ=3 | OUTREG=VGPR64_N() 
EASZ=2 | OUTREG=VGPR32_N()
EASZ=1 | OUTREG=VGPR32_N()

The register-width should scale by the effective operand-size instead of the address-size, like it is described in the documentation:

In 64-bit mode, the operand size is determined by the value of XOP.W. If XOP.W is 1, the operand size is 64-bit; if XOP.W is 0, the operand size is 32-bit. In 32-bit mode, XOP.W is ignored. 16-bit operands are not supported.

Besides that, XOP.W = 0 (W0) should be removed from the pattern.

It seems like (at least) all definitions defined in ‘amd-xop-isa.txt’ below BEXTR (including this one) are affected, but there might be more instructions with an incorrect W0 pattern.

[markcharney]

I have a small local patch for the first issue (EOSZ vs EASZ). The 2nd issue is a bit more invasive & I’m weighing approaches.

[markcharney]

rebased & merged. Let me know if you see further problems. Thanks for the bug report.