Incorrect operand-size for IP/EIP/RIP register?

I’m not sure if this is an actual issue, but I played with the JMP (0xE9) instruction and got the following results for the suppressed instruction-pointer operand in 32-bit mode:

1. xed-ex1 e900000000 -> REG0=EIP SUPPRESSED RW V 32 2. xed-ex1 66e900000000 -> REG0=EIP SUPPRESSED RW V 16 3. xed-ex1 67e900000000 -> REG0=IP SUPPRESSED RW V 32 4. xed-ex1 6766e900000000 -> REG0=IP SUPPRESSED RW V 16

Especially the third one looks fishy, because the operand-size is 32-bit, but the register (IP) itself is only 16-bits wide.

The Intel doc contains the following pseudo code, where EIP is always accessed as a full register (32-bit) regardless of the effective operand-size:

IF OperandSize = 32
  THEN
    EIP ← tempEIP;
  ELSE
    IF OperandSize = 16
      THEN (* OperandSize = 16 *)
        EIP ← tempEIP AND 0000FFFFH;
      ELSE (* OperandSize = 64)
        RIP ← tempRIP;
    FI;
FI;

Therefore I think the actual XED-operand-size for IP/EIP/RIP should always be the total width of the used register regardless of the effective-operand-size.

[markcharney]

Sorry about the delay. Pushed changes to master. Thanks for the issue(s). Let me know if you encounter any others!

[markcharney]

I have to review a bunch of instructions that use rIP() before I push my fix. Working on this…