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OpenSBI hangs during serial boot on Arty A7

See original GitHub issue

After loading bitstream (/make.py --board=arty --load), when serial booting (sudo lxterm --images=images/boot.json /dev/ttyUSB1 --serial-boot --speed=1e6) on Digilent Arty A7 OpenSBI appears to hang forever on sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver. Tried it out with both kernel versions from #164. Let me know if there is any additional information I can provide. Thanks for y’all’s awesome work on this!

--============= Liftoff! ===============--

OpenSBI v0.8-1-gecf7701
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name       : LiteX / VexRiscv-SMP
Platform Features   : timer,mfdeleg
Platform HART Count : 8
Boot HART ID        : 0
Boot HART ISA       : rv32imas
BOOT HART Features  : time
BOOT HART PMP Count : 0
Firmware Base       : 0x40f00000
Firmware Size       : 124 KB
Runtime SBI Version : 0.2

MIDELEG : 0x00000222
MEDELEG : 0x0000b101
[    0.000000] Linux version 5.11.0-rc2 (florent@panda) (riscv32-buildroot-linux-gnu-gcc.br_real (Buildroot 2020.11-281-g69e5046e7b) 10.2.0, GNU ld (GNU Binutils) 2.33.1) #2 SMP Mon Jan 11 10:05:20 CET 2021

...
[    1.606276] LiteX SoC Controller driver initialized: subreg:4, align:4
[    2.597710] f0001000.serial: ttyLXU0 at MMIO 0x0 (irq = 0, base_baud = 0) is a liteuart
[    2.602984] printk: console [liteuart0] enabled
[    2.602984] printk: console [liteuart0] enabled
[    2.605283] printk: bootconsole [sbi0] disabled
[    2.605283] printk: bootconsole [sbi0] disabled
[    2.623210] litex-spiflash f0006000.spiflash: s25fl128s1 (16384 Kbytes)
[    2.665384] libphy: Fixed MDIO Bus: probed
[    2.678509] liteeth f0004800.mac eth0: irq 2, mapped at a0415800
[    2.683099] i2c /dev entries driver
[    2.689960] i2c i2c-0: Not I2C compliant: can't read SCL
[    2.690861] i2c i2c-0: Bus may be unreliable
[    2.720638] litex-mmc f0006800.mmc: Requested clk_freq=12500000: set to 12500000 via div=8
[    2.749172] fpga_manager fpga0: LiteX ICAPBitstream FPGA Manager registered
[    2.773361] NET: Registered protocol family 10
[    2.788482] Segment Routing with IPv6
[    2.790187] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver

Issue Analytics

State:
Created 3 years ago
Comments:13 (7 by maintainers)

Top GitHub Comments

1reaction

enjoy-digitalcommented, Mar 11, 2021

@hasheddan: Good, to be sure I reused the Linux/OpenSBI images from #164 (but rebuilt the bitstream). So the difference with your previous tests is the bistream and rv32.dtb.

0reactions

enjoy-digitalcommented, Mar 26, 2021

Not sure what happened exactly, but I think we can close this since has been tested sucesfully with the re-generated bitstream and prebuilt images.

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