SDRAM initialization fails on some OrangeCrabs when LDM/UDM are used independently
See original GitHub issueI’m not sure where this bug belongs, but I found that a pre-built orangecrab image from https://github.com/litex-hub/linux-on-litex-vexriscv/issues/164 can’t initialize SDRAM:
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b0: |11100000| delays: 01+-01
m0, b1: |00000000| delays: -
m0, b2: |00000000| delays: -
m0, b3: |00000000| delays: -
best: m0, b00 delays: 01+-01
m1, b0: |11100000| delays: 02+-01
m1, b1: |00000000| delays: -
m1, b2: |00000000| delays: 00+-00
m1, b3: |00000000| delays: -
best: m1, b00 delays: 01+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
bus errors: 2/256
addr errors: 32/8192
data errors: 524279/524288
Memtest KO
Memory initialization failed
Same thing happens with a bitstream built with ./make.py --board=orangecrab --cpu-count=1 --build
.
I tried with two different OrangeCrab boards, the outcome is the same. The orangecrab target from litex-boards
works without problems.
Issue Analytics
- State:
- Created 3 years ago
- Comments:29 (21 by maintainers)
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The changes have been merged:
And the OrangeCrab bistream updated in https://github.com/litex-hub/linux-on-litex-vexriscv/issues/164.
A
git submodule update --init --recursive
will required inpythondata-cpu-vexriscv_smp
to fully update it. Thanks for the feedback/tests in this issue.@gregdavill: I’ve just been able to reproduce the issue on a Versa ECP5, so this probably has more chance to be related to the DM handling in the ECP5 LiteDRAM PHY than OC hardware (possible the DM swap does not help here, but this does not seem to be the root cause). I’ll try to investigate more (and it’s easier on the 45F of the Versa that has more room for LiteScope) but I have to work others priorities for now.