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Bool parameter for boolean VHDL generic produces wrong tcl command for Vivado.

See original GitHub issue

You can check it here: fusesoc_example. Just run fusesoc --cores-root . run --target custom_target_2 ::fusesoc_example and check file build/fusesoc_example_0/custom_target_2-vivado/fusesoc_example_0.tcl line 9.

There is: set_property generic {TOP_ADD_DELAY=1 } [get_filesets sources_1] Should be: set_property generic {TOP_ADD_DELAY=true } [get_filesets sources_1]

I could fix this if you tell me how/where the fix should be placed? In fusesoc or edalize?

Issue Analytics

State:
Created 4 years ago
Comments:9 (9 by maintainers)

Top GitHub Comments

1reaction

m-krucommented, Jun 26, 2019

I test with Vivado 2018.3, with True the build fails, with true it is successful. I am also astonished. Vivado output doesn’t explicitly inform that the problem is with True as the out in case of failed build is as follows:

# open_run impl_1
ERROR: [Common 17-69] Command failed: Run 'impl_1' has not been launched. Unable to open
INFO: [Common 17-206] Exiting Vivado at Wed Jun 26 07:14:52 2019...
make: *** [Makefile:6: fusesoc_example_0.bit] Error 1

To make the build successful I need to replace True with true. This is Xilinx. xilinx

0reactions

m-krucommented, Jun 26, 2019

Works.

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